[llvm-commits] [llvm] r59644 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td

[Stuart Hastings]

Author: stuart
Date: Wed Nov 19 11:19:35 2008
New Revision: 59644

URL: http://llvm.org/viewvc/llvm-project?rev=59644&view=rev
Log:
<rdar://problem/6351057>
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=59644&r1=59643&r2=59644&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Wed Nov 19 11:19:35 2008
@@ -226,10 +226,12 @@
 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
 // R8B, ... R15B. 
+// Allocate R12 and R13 last, as these require an extra byte when
+// encoded in x86_64 instructions.
 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
 def GR8 : RegisterClass<"X86", [i8],  8,
                         [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
-                         R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
+                         R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
@@ -240,12 +242,12 @@
       static const unsigned X86_GR8_AO_64_fp[] =
       {X86::AL,   X86::CL,   X86::DL,   X86::SIL, X86::DIL,
        X86::R8B,  X86::R9B,  X86::R10B, X86::R11B,
-       X86::BL,   X86::R12B, X86::R13B, X86::R14B, X86::R15B};
+       X86::BL,   X86::R14B, X86::R15B, X86::R12B, X86::R13B};
       // If not, just don't allocate SPL.
       static const unsigned X86_GR8_AO_64[] =
       {X86::AL,   X86::CL,   X86::DL,   X86::SIL, X86::DIL,
        X86::R8B,  X86::R9B,  X86::R10B, X86::R11B,
-       X86::BL,   X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::BPL};
+       X86::BL,   X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
       // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
       static const unsigned X86_GR8_AO_32[] =
       {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
@@ -281,7 +283,7 @@
 
 def GR16 : RegisterClass<"X86", [i16], 16,
                          [AX, CX, DX, SI, DI, BX, BP, SP,
-                          R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
+                          R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
   let SubRegClassList = [GR8];
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
@@ -293,14 +295,14 @@
       static const unsigned X86_GR16_AO_64_fp[] =
       {X86::AX,  X86::CX,   X86::DX,   X86::SI,   X86::DI,
        X86::R8W, X86::R9W,  X86::R10W, X86::R11W,
-       X86::BX,  X86::R12W, X86::R13W, X86::R14W, X86::R15W};
+       X86::BX, X86::R14W, X86::R15W,  X86::R12W, X86::R13W};
       static const unsigned X86_GR16_AO_32_fp[] =
       {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
       // If not, just don't allocate SPL.
       static const unsigned X86_GR16_AO_64[] =
       {X86::AX,  X86::CX,   X86::DX,   X86::SI,   X86::DI,
        X86::R8W, X86::R9W,  X86::R10W, X86::R11W,
-       X86::BX,  X86::R12W, X86::R13W, X86::R14W, X86::R15W, X86::BP};
+       X86::BX, X86::R14W, X86::R15W,  X86::R12W, X86::R13W, X86::BP};
       static const unsigned X86_GR16_AO_32[] =
       {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
 
@@ -345,7 +347,7 @@
 
 def GR32 : RegisterClass<"X86", [i32], 32, 
                          [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
-                          R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
+                          R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
   let SubRegClassList = [GR8, GR16];
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
@@ -357,14 +359,14 @@
       static const unsigned X86_GR32_AO_64_fp[] =
       {X86::EAX, X86::ECX,  X86::EDX,  X86::ESI,  X86::EDI,
        X86::R8D, X86::R9D,  X86::R10D, X86::R11D,
-       X86::EBX, X86::R12D, X86::R13D, X86::R14D, X86::R15D};
+       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
       static const unsigned X86_GR32_AO_32_fp[] =
       {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
       // If not, just don't allocate SPL.
       static const unsigned X86_GR32_AO_64[] =
       {X86::EAX, X86::ECX,  X86::EDX,  X86::ESI,  X86::EDI,
        X86::R8D, X86::R9D,  X86::R10D, X86::R11D,
-       X86::EBX, X86::R12D, X86::R13D, X86::R14D, X86::R15D, X86::EBP};
+       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
       static const unsigned X86_GR32_AO_32[] =
       {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
 
@@ -409,7 +411,7 @@
 
 def GR64 : RegisterClass<"X86", [i64], 64, 
                          [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
-                          RBX, R12, R13, R14, R15, RBP, RSP]> {
+                          RBX, R14, R15, R12, R13, RBP, RSP]> {
   let SubRegClassList = [GR8, GR16, GR32];
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;