[llvm-commits] [llvm] r59120 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp test/CodeGen/Alpha/2008-11-12-Add128.ll

[Duncan Sands]

Author: baldrick
Date: Wed Nov 12 02:23:26 2008
New Revision: 59120

URL: http://llvm.org/viewvc/llvm-project?rev=59120&view=rev
Log:
Correct some thinkos in the expansion of ADD/SUB
when the target does not support ADDC/SUBC.  This
fixes PR3044.

Added:
    llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=59120&r1=59119&r2=59120&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Nov 12 02:23:26 2008
@@ -1228,7 +1228,6 @@
   GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
 
   MVT NVT = LHSL.getValueType();
-  SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
   SDValue LoOps[2] = { LHSL, RHSL };
   SDValue HiOps[3] = { LHSH, RHSH };
 
@@ -1242,6 +1241,7 @@
                          TLI.getTypeToExpandTo(NVT));
 
   if (hasCarry) {
+    SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
     if (N->getOpcode() == ISD::ADD) {
       Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
       HiOps[2] = Lo.getValue(1);
@@ -1253,8 +1253,8 @@
     }
   } else {
     if (N->getOpcode() == ISD::ADD) {
-      Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
-      Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
+      Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
+      Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
       SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
                                   ISD::SETULT);
       SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
@@ -1266,9 +1266,10 @@
                                    DAG.getConstant(1, NVT), Carry1);
       Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
     } else {
-      Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
-      Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
-      SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
+      Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
+      Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
+      SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]),
+                                 LoOps[0], LoOps[1], ISD::SETULT);
       SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
                                    DAG.getConstant(1, NVT),
                                    DAG.getConstant(0, NVT));

Added: llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll?rev=59120&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll (added)
+++ llvm/trunk/test/CodeGen/Alpha/2008-11-12-Add128.ll Wed Nov 12 02:23:26 2008
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc
+; PR3044
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+target triple = "alphaev6-unknown-linux-gnu"
+
+define i128 @__mulvti3(i128 %u, i128 %v) nounwind {
+entry:
+	%0 = load i128* null, align 16		; <i128> [#uses=1]
+	%1 = load i64* null, align 8		; <i64> [#uses=1]
+	%2 = zext i64 %1 to i128		; <i128> [#uses=1]
+	%3 = add i128 %2, %0		; <i128> [#uses=1]
+	store i128 %3, i128* null, align 16
+	unreachable
+}