[llvm-commits] [llvm] r58793 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.h ARMInstrInfo.td
Evan Cheng
evan.cheng at apple.com
Wed Nov 5 19:35:07 PST 2008
Author: evancheng
Date: Wed Nov 5 21:35:07 2008
New Revision: 58793
URL: http://llvm.org/viewvc/llvm-project?rev=58793&view=rev
Log:
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=58793&r1=58792&r2=58793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 5 21:35:07 2008
@@ -21,26 +21,22 @@
def Pseudo : Format<1>;
def MulFrm : Format<2>;
-def MulSMLAW : Format<3>;
-def MulSMULW : Format<4>;
-def MulSMLA : Format<5>;
-def MulSMUL : Format<6>;
-def Branch : Format<7>;
-def BranchMisc : Format<8>;
-
-def DPFrm : Format<9>;
-def DPSoRegFrm : Format<10>;
-
-def LdFrm : Format<11>;
-def StFrm : Format<12>;
-def LdMiscFrm : Format<13>;
-def StMiscFrm : Format<14>;
-def LdMulFrm : Format<15>;
-def StMulFrm : Format<16>;
-
-def ArithMisc : Format<17>;
-def ThumbFrm : Format<18>;
-def VFPFrm : Format<19>;
+def Branch : Format<3>;
+def BranchMisc : Format<4>;
+
+def DPFrm : Format<5>;
+def DPSoRegFrm : Format<6>;
+
+def LdFrm : Format<7>;
+def StFrm : Format<8>;
+def LdMiscFrm : Format<9>;
+def StMiscFrm : Format<10>;
+def LdMulFrm : Format<11>;
+def StMulFrm : Format<12>;
+
+def ArithMisc : Format<13>;
+def ThumbFrm : Format<14>;
+def VFPFrm : Format<15>;
// Misc flag for data processing instructions that indicates whether
// the instruction has a Rn register operand.
@@ -704,6 +700,17 @@
let Inst{27-21} = mulopc;
}
+// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
+class AMulxyI<bits<7> mulopc, dag oops, dag iops, string opc,
+ string asm, list<dag> pattern>
+ : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
+ asm,"",pattern> {
+ let Inst{4} = 0;
+ let Inst{7} = 1;
+ let Inst{20} = 0;
+ let Inst{27-21} = mulopc;
+}
+
//===----------------------------------------------------------------------===//
// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=58793&r1=58792&r2=58793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Wed Nov 5 21:35:07 2008
@@ -74,42 +74,38 @@
// Instruction encoding formats.
//
FormShift = 14,
- FormMask = 0x1f << FormShift,
+ FormMask = 0xf << FormShift,
// Pseudo instructions
Pseudo = 1 << FormShift,
// Multiply instructions
MulFrm = 2 << FormShift,
- MulSMLAW = 3 << FormShift,
- MulSMULW = 4 << FormShift,
- MulSMLA = 5 << FormShift,
- MulSMUL = 6 << FormShift,
// Branch instructions
- Branch = 7 << FormShift,
- BranchMisc = 8 << FormShift,
+ Branch = 3 << FormShift,
+ BranchMisc = 4 << FormShift,
// Data Processing instructions
- DPFrm = 9 << FormShift,
- DPSoRegFrm = 10 << FormShift,
+ DPFrm = 5 << FormShift,
+ DPSoRegFrm = 6 << FormShift,
// Load and Store
- LdFrm = 11 << FormShift,
- StFrm = 12 << FormShift,
- LdMiscFrm = 13 << FormShift,
- StMiscFrm = 14 << FormShift,
- LdMulFrm = 15 << FormShift,
- StMulFrm = 16 << FormShift,
+ LdFrm = 7 << FormShift,
+ StFrm = 8 << FormShift,
+ LdMiscFrm = 9 << FormShift,
+ StMiscFrm = 10 << FormShift,
+ LdMulFrm = 11 << FormShift,
+ StMulFrm = 12 << FormShift,
// Miscellaneous arithmetic instructions
- ArithMisc = 17 << FormShift,
+ ArithMisc = 13 << FormShift,
// Thumb format
- ThumbFrm = 18 << FormShift,
+ ThumbFrm = 14 << FormShift,
// VFP format
- VPFFrm = 19 << FormShift,
+ VPFFrm = 15 << FormShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=58793&r1=58792&r2=58793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 5 21:35:07 2008
@@ -962,87 +962,121 @@
// FIXME: encoding
multiclass AI_smul<string opc, PatFrag opnode> {
- def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
+ def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "bb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 0;
+ }
- def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
+ def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "bt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, 16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 1;
+ }
- def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
+ def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "tb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
(sext_inreg GPR:$b, i16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 0;
+ }
- def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
+ def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "tt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
(sra GPR:$b, 16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 1;
+ }
- def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
+ def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "wb"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), 16))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 0;
+ }
- def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
+ def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "wt"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sra GPR:$b, 16)), 16))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 1;
+ }
}
// FIXME: encoding
multiclass AI_smla<string opc, PatFrag opnode> {
- def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
+ def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc,
(opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16))))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 0;
+ }
- def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
+ def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "bt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, 16))))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 1;
+ }
- def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
+ def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "tb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
(sext_inreg GPR:$b, i16))))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 0;
+ }
- def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
+ def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "tt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
(sra GPR:$b, 16))))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 1;
+ let Inst{6} = 1;
+ }
- def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
+ def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "wb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), 16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 0;
+ }
- def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
+ def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "wt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sra GPR:$b, 16)), 16)))]>,
- Requires<[IsARM, HasV5TE]>;
+ Requires<[IsARM, HasV5TE]> {
+ let Inst{5} = 0;
+ let Inst{6} = 1;
+ }
}
-// FIXME: encoding
defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
-// FIXME: encoding
defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// TODO: Halfword multiple accumulate long: SMLAL<x><y>
More information about the llvm-commits
mailing list