[llvm-commits] [llvm] r57708 - in /llvm/branches/release_24: lib/CodeGen/VirtRegMap.cpp test/CodeGen/X86/2008-10-16-SpillerBug.ll

[Tanya Lattner]

Author: tbrethou
Date: Fri Oct 17 13:10:12 2008
New Revision: 57708

URL: http://llvm.org/viewvc/llvm-project?rev=57708&view=rev
Log:
Merge from mainline..

Added:
    llvm/branches/release_24/test/CodeGen/X86/2008-10-16-SpillerBug.ll
      - copied unchanged from r57673, llvm/trunk/test/CodeGen/X86/2008-10-16-SpillerBug.ll
Modified:
    llvm/branches/release_24/lib/CodeGen/VirtRegMap.cpp

Modified: llvm/branches/release_24/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_24/lib/CodeGen/VirtRegMap.cpp?rev=57708&r1=57707&r2=57708&view=diff

==============================================================================
--- llvm/branches/release_24/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/branches/release_24/lib/CodeGen/VirtRegMap.cpp Fri Oct 17 13:10:12 2008
@@ -635,7 +635,8 @@
 /// marked kill, then it must be due to register reuse. Transfer the kill info
 /// over.
 static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
-                        std::vector<MachineOperand*> &KillOps) {
+                        std::vector<MachineOperand*> &KillOps,
+                        const TargetRegisterInfo* TRI) {
   const TargetInstrDesc &TID = MI.getDesc();
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
@@ -669,6 +670,11 @@
     unsigned Reg = MO.getReg();
     RegKills.reset(Reg);
     KillOps[Reg] = NULL;
+    // It also defines (or partially define) aliases.
+    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+      RegKills.reset(*AS);
+      KillOps[*AS] = NULL;
+    }
   }
 }
 
@@ -839,7 +845,7 @@
             
             Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
             --MII;
-            UpdateKills(*MII, RegKills, KillOps);
+            UpdateKills(*MII, RegKills, KillOps, TRI);
             DOUT << '\t' << *MII;
             
             DOUT << "Reuse undone!\n";
@@ -1283,7 +1289,7 @@
         }
         // This invalidates Phys.
         Spills.ClobberPhysReg(Phys);
-        UpdateKills(*prior(MII), RegKills, KillOps);
+        UpdateKills(*prior(MII), RegKills, KillOps, TRI);
         DOUT << '\t' << *prior(MII);
       }
     }
@@ -1500,7 +1506,7 @@
         TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
 
         MachineInstr *CopyMI = prior(MII);
-        UpdateKills(*CopyMI, RegKills, KillOps);
+        UpdateKills(*CopyMI, RegKills, KillOps, TRI);
 
         // This invalidates DesignatedReg.
         Spills.ClobberPhysReg(DesignatedReg);
@@ -1550,7 +1556,7 @@
         MI.getOperand(i).setIsKill();
       unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
       MI.getOperand(i).setReg(RReg);
-      UpdateKills(*prior(MII), RegKills, KillOps);
+      UpdateKills(*prior(MII), RegKills, KillOps, TRI);
       DOUT << '\t' << *prior(MII);
     }
 
@@ -1650,7 +1656,7 @@
             // super-register is needed below.
             if (KillOpnd && !KillOpnd->getSubReg() &&
                 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
-              MBB.insert(MII, NewMIs[0]);
+             MBB.insert(MII, NewMIs[0]);
               NewStore = NewMIs[1];
               MBB.insert(MII, NewStore);
               VRM.addSpillSlotUse(SS, NewStore);
@@ -1825,7 +1831,7 @@
             VRM.RemoveMachineInstrFromMaps(&MI);
             MBB.erase(&MI);
             Erased = true;
-            UpdateKills(*LastStore, RegKills, KillOps);
+            UpdateKills(*LastStore, RegKills, KillOps, TRI);
             goto ProcessNextInst;
           }
         }
@@ -1835,7 +1841,7 @@
     DistanceMap.insert(std::make_pair(&MI, Dist++));
     if (!Erased && !BackTracked) {
       for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
-        UpdateKills(*II, RegKills, KillOps);
+        UpdateKills(*II, RegKills, KillOps, TRI);
     }
     MII = NextMII;
   }