[llvm-commits] [llvm] r57262 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Chris Lattner]

On Oct 7, 2008, at 2:08 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Tue Oct  7 16:08:09 2008
> New Revision: 57262
>
> URL: http://llvm.org/viewvc/llvm-project?rev=57262&view=rev
> Log:
> Unconditional branch instruction encoding fix. Needs to use ABI, not  
> AXI, to get the proper opcode bits.

Hi Jim,

> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct  7 16:08:09 2008
> @@ -567,7 +567,7 @@
>   // B is "predicable" since it can be xformed into a Bcc.
>   let isBarrier = 1 in {
>     let isPredicable = 1 in
> -    def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b  
> $target",
> +    def B : ABI<{0,1,0,1}, (outs), (ins brtarget:$target), Branch,  
> "b $target",
>                 [(br bb:$target)]>;

I assume you're changing 0xA to 0,1,0,1 due to an endianness issue?   
Why not just change the ABI/AXI patterns to do the bit swapping?  I'd  
strongly prefer to have all the instructions (like B) have clear and  
easy to understand encodings in them.  I'd rather push any complexity/ 
weirdness up into parent tblgen classes.

-Chris

>
>
>   let isNotDuplicable = 1, isIndirectBranch = 1 in {
>
>
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