[llvm-commits] [llvm] r57257 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td

[Evan Cheng]

On Oct 7, 2008, at 2:21 PM, Dale Johannesen wrote:

>
> On Oct 7, 2008, at 2:15 PMPDT, Evan Cheng wrote:
>
>>
>> On Oct 7, 2008, at 2:03 PM, Dan Gohman wrote:
>>
>>> This looks like the same problem I found related to how fast-isel
>>> emits shifts. The local register allocator's liveness code
>>> does not check aliases or subregisters at all right now.
>>
>> That needs to be fixed.
>>
>>>
>>>
>>> We could fix it, but on the other hand it's arguably sloppy for
>>> instruction selectors to not precisely describe their physical
>>> register uses.
>>
>> I agree. In this case DVI8r should say it defines AL, AH and uses AL,
>> AH which makes it clear it reads 2 values and outputs 2.
>
> No, it reads 1 value and outputs two.  It is not the same as DIV16 and
> DIV32.
> The way I have it matches Intel docs.

Ok. It's good to match what Intel manual says. But that's additional  
goodness. Previously DIV16r is marked as using AL, AH and the implicit  
use is copied to AX. While this is not ideal, it's not incorrect.  
Local liveness cannot mark AX as dead.

Evan


>
>
>> On the other
>> hand, it should not matter if it says it uses AX which is the same as
>> AL + AH.
>>
>> Evan
>>
>>>
>>>
>>> Dan
>>>
>>> On Oct 7, 2008, at 1:34 PM, Evan Cheng wrote:
>>>
>>>> Hi Dale,
>>>>
>>>> I think we ought to fix the bug in the local register allocator
>>>> instead. Is it not checking for aliases or sub-registers somewhere?
>>>>
>>>> Thanks,
>>>>
>>>> Evan
>>>>
>>>> On Oct 7, 2008, at 11:54 AM, Dale Johannesen wrote:
>>>>
>>>>> Author: johannes
>>>>> Date: Tue Oct  7 13:54:28 2008
>>>>> New Revision: 57257
>>>>>
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=57257&view=rev
>>>>> Log:
>>>>> Model hardwired inputs & outputs of x86 8-bit divides correctly.
>>>>> Fixes local RA miscompilation of gcc.c-torture/execute/
>>>>> 20020904-1.c -
>>>>> O0.
>>>>>
>>>>>
>>>>> Modified:
>>>>> llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>>>>
>>>>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=57257&r1=57256&r2=57257&view=diff
>>>>>
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> =
>>>>> = 
>>>>> ==================================================================
>>>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>>>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Oct  7 13:54:28
>>>>> 2008
>>>>> @@ -728,7 +728,7 @@
>>>>> }
>>>>>
>>>>> // unsigned division/remainder
>>>>> -let Defs = [AX,EFLAGS], Uses = [AL,AH] in
>>>>> +let Defs = [AL,AH,EFLAGS], Uses = [AX] in
>>>>> def DIV8r  : I<0xF6, MRM6r, (outs),  (ins GR8:$src),          //
>>>>> AX/
>>>>> r8 = AL,AH
>>>>>            "div{b}\t$src", []>;
>>>>> let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
>>>>> @@ -738,7 +738,7 @@
>>>>> def DIV32r : I<0xF7, MRM6r, (outs),  (ins GR32:$src),         //
>>>>> EDX:EAX/r32 = EAX,EDX
>>>>>            "div{l}\t$src", []>;
>>>>> let mayLoad = 1 in {
>>>>> -let Defs = [AX,EFLAGS], Uses = [AL,AH] in
>>>>> +let Defs = [AL,AH,EFLAGS], Uses = [AX] in
>>>>> def DIV8m  : I<0xF6, MRM6m, (outs), (ins i8mem:$src),       // AX/
>>>>> [mem8] = AL,AH
>>>>>            "div{b}\t$src", []>;
>>>>> let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
>>>>> @@ -750,7 +750,7 @@
>>>>> }
>>>>>
>>>>> // Signed division/remainder.
>>>>> -let Defs = [AX,EFLAGS], Uses = [AL,AH] in
>>>>> +let Defs = [AL,AH,EFLAGS], Uses = [AX] in
>>>>> def IDIV8r : I<0xF6, MRM7r, (outs),  (ins GR8:$src),          //
>>>>> AX/
>>>>> r8 = AL,AH
>>>>>            "idiv{b}\t$src", []>;
>>>>> let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
>>>>> @@ -760,7 +760,7 @@
>>>>> def IDIV32r: I<0xF7, MRM7r, (outs),  (ins GR32:$src),         //
>>>>> EDX:EAX/r32 = EAX,EDX
>>>>>            "idiv{l}\t$src", []>;
>>>>> let mayLoad = 1, mayLoad = 1 in {
>>>>> -let Defs = [AX,EFLAGS], Uses = [AL,AH] in
>>>>> +let Defs = [AL,AH,EFLAGS], Uses = [AX] in
>>>>> def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src),      // AX/
>>>>> [mem8] = AL,AH
>>>>>            "idiv{b}\t$src", []>;
>>>>> let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
>>>>>
>>>>>
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