[llvm-commits] [llvm] r57258 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.h

[Jim Grosbach]

Author: grosbach
Date: Tue Oct  7 14:05:35 2008
New Revision: 57258

URL: http://llvm.org/viewvc/llvm-project?rev=57258&view=rev
Log:
Encode the conditional execution predicate when JITing.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.h

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=57258&r1=57257&r2=57258&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Oct  7 14:05:35 2008
@@ -256,8 +256,8 @@
 unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
                                                     const TargetInstrDesc &TID,
                                                     unsigned Binary) {
-  // FIXME: Assume CC is AL for now.
-  Binary |= ARMCC::AL << 28;
+  // Set the conditional execution predicate
+  Binary |= II->getPredicate(&MI) << 28;
 
   switch (TID.TSFlags & ARMII::FormMask) {
   default:
@@ -376,8 +376,8 @@
 unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
                                                  const TargetInstrDesc &TID,
                                                  unsigned Binary) {
-  // FIXME: Assume CC is AL for now.
-  Binary |= ARMCC::AL << 28;
+  // Set the conditional execution predicate
+  Binary |= II->getPredicate(&MI) << 28;
 
   // Encode S bit if MI modifies CPSR.
   Binary |= getAddrMode1SBit(MI, TID);
@@ -429,8 +429,8 @@
 unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
                                                  const TargetInstrDesc &TID,
                                                  unsigned Binary) {
-  // FIXME: Assume CC is AL for now.
-  Binary |= ARMCC::AL << 28;
+  // Set the conditional execution predicate
+  Binary |= II->getPredicate(&MI) << 28;
 
   // Set first operand
   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@@ -470,8 +470,8 @@
 unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
                                                  const TargetInstrDesc &TID,
                                                  unsigned Binary) {
-  // FIXME: Assume CC is AL for now.
-  Binary |= ARMCC::AL << 28;
+  // Set the conditional execution predicate
+  Binary |= II->getPredicate(&MI) << 28;
 
   // Set first operand
   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@@ -507,8 +507,8 @@
 unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
                                                  const TargetInstrDesc &TID,
                                                  unsigned Binary) {
-  // FIXME: Assume CC is AL for now.
-  Binary |= ARMCC::AL << 28;
+  // Set the conditional execution predicate
+  Binary |= II->getPredicate(&MI) << 28;
 
   // Set first operand
   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=57258&r1=57257&r2=57258&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Tue Oct  7 14:05:35 2008
@@ -217,6 +217,12 @@
   // Predication support.
   virtual bool isPredicated(const MachineInstr *MI) const;
 
+  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
+    int PIdx = MI->findFirstPredOperandIdx();
+    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 
+                      : ARMCC::AL;
+  }
+
   virtual
   bool PredicateInstruction(MachineInstr *MI,
                             const SmallVectorImpl<MachineOperand> &Pred) const;