[llvm-commits] [llvm] r57252 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Tue Oct  7 12:42:09 2008
New Revision: 57252

URL: http://llvm.org/viewvc/llvm-project?rev=57252&view=rev
Log:
Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=57252&r1=57251&r2=57252&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Oct  7 12:42:09 2008
@@ -392,14 +392,11 @@
 
   // Encode first non-shifter register operand if there is one.
   unsigned Format = TID.TSFlags & ARMII::FormMask;
-  bool isUnary = (Format == ARMII::DPRdMisc  ||
-                  Format == ARMII::DPRdIm    ||
-                  Format == ARMII::DPRdReg   ||
-                  Format == ARMII::DPRdSoReg ||
-                  Format == ARMII::DPRnIm    ||
-                  Format == ARMII::DPRnReg   ||
-                  Format == ARMII::DPRnSoReg);
-  if (!isUnary) {
+  bool hasRnOperand= !(Format == ARMII::DPRdMisc  ||
+                       Format == ARMII::DPRdIm    ||
+                       Format == ARMII::DPRdReg   ||
+                       Format == ARMII::DPRdSoReg);
+  if (hasRnOperand) {
     Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
     ++OpIdx;
   }