[llvm-commits] [llvm] r56911 - in /llvm/trunk/lib/Target/X86: X86Instr64bit.td X86InstrInfo.td

[Evan Cheng]

Hmmm. There could be more bugs of the kind. Any instruction that  
touches a non-allocatable register should not be deleted. If your DCE  
is not checking that, then we need to make sure all instructions that  
touch esp, etc. should mark these uses.

Evan

On Oct 1, 2008, at 9:08 AM, Dan Gohman wrote:

> Yes. Sorry for the terse commit message. It fixes
> a DeadMachineInstructionElim bug, where it was deleting
> stack-pointer assignments because they appeared to be dead.
> Neither bugpoint or I were able to reduce the testcase,
> but the problem is visible in 403.gcc on x86-64.
>
> Dan
>
> On Tue, September 30, 2008 9:35 pm, Evan Cheng wrote:
>> Is this fixing a fast-isel bug?
>>
>> Evan
>>
>> On Sep 30, 2008, at 9:14 PM, Dan Gohman wrote:
>>
>>> Author: djg
>>> Date: Tue Sep 30 23:14:30 2008
>>> New Revision: 56911
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=56911&view=rev
>>> Log:
>>> Mark CALL instructions as having a Use of ESP/RSP.
>>>
>>> Modified:
>>>   llvm/trunk/lib/Target/X86/X86Instr64bit.td
>>>   llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=56911&r1=56910&r2=56911&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
>>> +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Sep 30 23:14:30
>>> 2008
>>> @@ -95,7 +95,8 @@
>>>              FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
>>>              MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
>>>              XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
>>> -              XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
>>> EFLAGS] in {
>>> +              XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
>>> EFLAGS],
>>> +      Uses = [RSP] in {
>>>    def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst,
>>> variable_ops),
>>>                          "call\t${dst:call}", []>;
>>>    def CALL64r       : I<0xFF, MRM2r, (outs), (ins GR64:$dst,
>>> variable_ops),
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=56911&r1=56910&r2=56911&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 30 23:14:30  
>>> 2008
>>> @@ -334,7 +334,7 @@
>>>  def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
>>>
>>> // PIC base
>>> -let neverHasSideEffects = 1, isNotDuplicable = 1 in
>>> +let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
>>>  def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:
>>> $label),
>>>                      "call\t$label\n\tpop{l}\t$reg", []>;
>>>
>>> @@ -414,7 +414,8 @@
>>>  // All calls clobber the non-callee saved registers...
>>>  let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
>>>              MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
>>> -              XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
>>> EFLAGS] in {
>>> +              XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
>>> EFLAGS],
>>> +      Uses = [ESP] in {
>>>    def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:
>>> $dst,variable_ops),
>>>                           "call\t${dst:call}", []>;
>>>    def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst,
>>> variable_ops),
>>>
>>>
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