[llvm-commits] [llvm] r56326 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp

[Chris Lattner]

On Sep 22, 2008, at 10:10 AM, Evan Cheng wrote:
>>> %1 and %2 can share a register, but if there is no way to  
>>> distinguish
>>> between earlyclobber and overlaps-earlyclobber, we can't do this.
>>> In theory this is a matter of correctness, it is possible to
>>> construct
>>> cases where you run out of registers if you don't share.
>>
>> I don't get this at all.  How can a *live interval* be an
>> earlyclobber?  It seems that the easy and natural way to model this  
>> is
>> that the def starts one notch earlier in the use slot of an
>> instruction, instead of it's normal place (the def slot).
>>
>> In other words, I don't understand why this needs to be modeled
>> explicitly in live intervals, the construction of live intervals
>> should just handle the early clobber def as starting one slot early.
>
> As I said in another email, that's the right solution except it breaks
> liveintervalanalysis and coalescer assumptions.

Ok, which assumptions?  Can you please point out an example in the code?

> It's possible to try
> that approach but we don't have enough test coverage for early  
> clobber.

We actually have quite a bit of code that uses earlyclobber asms (and  
have even found bugs in apps that didn't use earlyclobber where it was  
supposed to), it is just that they are mostly correctly handled by the  
hacky code in sdisel.  Once that code is removed, early clobber  
support will start getting more testing.

-Chris