[llvm-commits] [llvm] r56384 - in /llvm/trunk/lib/CodeGen: RegAllocLinearScan.cpp SimpleRegisterCoalescing.cpp

[Evan Cheng]

On Sep 21, 2008, at 8:26 PM, Chris Lattner wrote:

> On Sep 21, 2008, at 7:41 PM, Evan Cheng wrote:
>>> If you model the early clobber def as starting one slot early, it
>>> will
>>> explicitly conflict with all inputs to the asm, and this can be
>>> backed
>>> out.
>>
>> While that's the correct approach, it breaks all kinds of assumptions
>> in liveintervals and the coalescer. It will make the problem much  
>> more
>> complicated. I don't think it's worth the effort.
>
> What sorts of assumptions?

That use must be 1 cycle after instruction cycle, def must be 2 cycles  
after it.

>
>
>> Besides, from uArch point of view, "early clobber" is totally bogus.
>> It should really be "no read bypass". The correct way to model it
>> would be to delay read by one cycle.
>
> It typically doesn't have anything to do with a micro architecture, it
> has to do with the fact that an inline asm has multiple instructions.
> For example if you had an inline asm with:
>
>   "$out0 = inst1 $in1, 4
>    $out1 = inst2 $in2, 142"
>
> Then you'd have to mark $out0 as being an early clobber, because it is
> stored to before $in2 is read.

Ewwww.

Evan

>
>
> -Chris
>
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