[llvm-commits] [llvm] r56388 - /llvm/trunk/include/llvm/CodeGen/LiveInterval.h

[Dale Johannesen]

Author: johannes
Date: Sat Sep 20 12:45:21 2008
New Revision: 56388

URL: http://llvm.org/viewvc/llvm-project?rev=56388&view=rev
Log:
Shorten and rearrange data fields to save a word of memory.
Per review feedback.


Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=56388&r1=56387&r2=56388&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Sat Sep 20 12:45:21 2008
@@ -103,19 +103,20 @@
 
     unsigned reg;        // the register or stack slot of this interval
                          // if the top bits is set, it represents a stack slot.
-    unsigned preference; // preferred register to allocate for this interval
     float weight;        // weight of this interval
-    bool isEarlyClobber;
-    bool overlapsEarlyClobber;
+    // The next 3 fields pack into a single word (on most hosts).
+    // Logically the first two could be bitfields, but that's slower.
+    bool isEarlyClobber;  // marked earlyclobber in some asm
+    bool overlapsEarlyClobber; // input to asm that has an earlyclobber
+    unsigned short preference; // preferred register for this interval
     Ranges ranges;       // the ranges in which this register is live
     VNInfoList valnos;   // value#'s
 
   public:
     LiveInterval(unsigned Reg, float Weight, bool IsSS = false, 
                  bool IsEarlyClobber = false, bool OverlapsEarlyClobber = false)
-      : reg(Reg), preference(0), weight(Weight), 
-        isEarlyClobber(IsEarlyClobber), 
-        overlapsEarlyClobber(OverlapsEarlyClobber) {
+      : reg(Reg), weight(Weight), isEarlyClobber(IsEarlyClobber), 
+        overlapsEarlyClobber(OverlapsEarlyClobber), preference(0)  {
       if (IsSS)
         reg = reg | (1U << (sizeof(unsigned)*8-1));
     }