[llvm-commits] [llvm] r56112 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2008-09-11-CoalescerBug.ll

[Evan Cheng]

Author: evancheng
Date: Thu Sep 11 13:40:32 2008
New Revision: 56112

URL: http://llvm.org/viewvc/llvm-project?rev=56112&view=rev
Log:
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.

Added:
    llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=56112&r1=56111&r2=56112&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Sep 11 13:40:32 2008
@@ -1319,7 +1319,8 @@
 
   // If resulting interval has a preference that no longer fits because of subreg
   // coalescing, just clear the preference.
-  if (ResDstInt->preference && (isExtSubReg || isInsSubReg)) {
+  if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
+      TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
     const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
     if (!RC->contains(ResDstInt->preference))
       ResDstInt->preference = 0;

Added: llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug.ll?rev=56112&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-09-11-CoalescerBug.ll Thu Sep 11 13:40:32 2008
@@ -0,0 +1,38 @@
+; RUN: llvm-as < %s | llc -march=x86
+; PR2783
+
+ at g_15 = external global i16		; <i16*> [#uses=2]
+
+define i32 @func_3(i32 %p_5) nounwind {
+entry:
+	%0 = srem i32 1, 0		; <i32> [#uses=2]
+	%1 = load i16* @g_15, align 2		; <i16> [#uses=1]
+	%2 = zext i16 %1 to i32		; <i32> [#uses=1]
+	%3 = and i32 %2, 1		; <i32> [#uses=1]
+	%4 = tail call i32 (...)* @rshift_u_s( i32 1 ) nounwind		; <i32> [#uses=1]
+	%5 = icmp slt i32 %4, 2		; <i1> [#uses=1]
+	%6 = zext i1 %5 to i32		; <i32> [#uses=1]
+	%7 = icmp sge i32 %3, %6		; <i1> [#uses=1]
+	%8 = zext i1 %7 to i32		; <i32> [#uses=1]
+	%9 = load i16* @g_15, align 2		; <i16> [#uses=1]
+	%10 = icmp eq i16 %9, 0		; <i1> [#uses=1]
+	%11 = zext i1 %10 to i32		; <i32> [#uses=1]
+	%12 = tail call i32 (...)* @func_20( i32 1 ) nounwind		; <i32> [#uses=1]
+	%13 = icmp sge i32 %11, %12		; <i1> [#uses=1]
+	%14 = zext i1 %13 to i32		; <i32> [#uses=1]
+	%15 = sub i32 %8, %14		; <i32> [#uses=1]
+	%16 = icmp ult i32 %15, 2		; <i1> [#uses=1]
+	%17 = zext i1 %16 to i32		; <i32> [#uses=1]
+	%18 = icmp ugt i32 %0, 3		; <i1> [#uses=1]
+	%or.cond = or i1 false, %18		; <i1> [#uses=1]
+	%19 = select i1 %or.cond, i32 0, i32 %0		; <i32> [#uses=1]
+	%.0 = lshr i32 %17, %19		; <i32> [#uses=1]
+	%20 = tail call i32 (...)* @func_7( i32 %.0 ) nounwind		; <i32> [#uses=0]
+	ret i32 undef
+}
+
+declare i32 @rshift_u_s(...)
+
+declare i32 @func_20(...)
+
+declare i32 @func_7(...)