[llvm-commits] [llvm] r55877 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-trunc.ll

[Evan Cheng]

Author: evancheng
Date: Sun Sep  7 03:47:42 2008
New Revision: 55877

URL: http://llvm.org/viewvc/llvm-project?rev=55877&view=rev
Log:
Handle x86 truncate to i8 with target hook for now.

Added:
    llvm/trunk/test/CodeGen/X86/fast-isel-trunc.ll
Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=55877&r1=55876&r2=55877&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Sun Sep  7 03:47:42 2008
@@ -65,6 +65,8 @@
 
   bool X86SelectSelect(Instruction *I);
 
+  bool X86SelectTrunc(Instruction *I);
+
   unsigned TargetMaterializeConstant(Constant *C, MachineConstantPool* MCP);
 };
 
@@ -557,6 +559,40 @@
   return true;
 }
 
+bool X86FastISel::X86SelectTrunc(Instruction *I) {
+  if (Subtarget->is64Bit())
+    // All other cases should be handled by the tblgen generated code.
+    return false;
+  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+  MVT DstVT = TLI.getValueType(I->getType());
+  if (DstVT != MVT::i8)
+    // All other cases should be handled by the tblgen generated code.
+    return false;
+  if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
+    // All other cases should be handled by the tblgen generated code.
+    return false;
+
+  unsigned InputReg = getRegForValue(I->getOperand(0));
+  if (!InputReg)
+    // Unhandled operand.  Halt "fast" selection and bail.
+    return false;
+
+  // First issue a copy to GR16_ or GR32_.
+  unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
+  const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
+    ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
+  unsigned CopyReg = createResultReg(CopyRC);
+  BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
+
+  // Then issue an extract_subreg.
+  unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg,1); // x86_subreg_8bit
+  if (!ResultReg)
+    return false;
+
+  UpdateValueMap(I, ResultReg);
+  return true;
+}
+
 bool
 X86FastISel::TargetSelectInstruction(Instruction *I)  {
   switch (I->getOpcode()) {
@@ -578,6 +614,8 @@
     return X86SelectShift(I);
   case Instruction::Select:
     return X86SelectSelect(I);
+  case Instruction::Trunc:
+    return X86SelectTrunc(I);
   }
 
   return false;

Added: llvm/trunk/test/CodeGen/X86/fast-isel-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-trunc.ll?rev=55877&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-trunc.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-trunc.ll Sun Sep  7 03:47:42 2008
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=x86 -fast-isel
+; RUN: llvm-as < %s | llc -march=x86-64 -fast-isel
+
+define i8 @t1(i32 %x) signext nounwind  {
+	%tmp1 = trunc i32 %x to i8
+	ret i8 %tmp1
+}
+
+define i8 @t2(i16 signext %x) signext nounwind  {
+	%tmp1 = trunc i16 %x to i8
+	ret i8 %tmp1
+}