[llvm-commits] [llvm] r55623 - in /llvm/trunk: lib/Target/Alpha/AlphaCodeEmitter.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp utils/TableGen/CodeEmitterGen.cpp

[Evan Cheng]

Author: evancheng
Date: Tue Sep  2 01:51:36 2008
New Revision: 55623

URL: http://llvm.org/viewvc/llvm-project?rev=55623&view=rev
Log:
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.

Modified:
    llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/CodeEmitterGen.cpp

Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=55623&r1=55622&r2=55623&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Tue Sep  2 01:51:36 2008
@@ -33,7 +33,8 @@
 
     /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
     ///
-    int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+    unsigned getMachineOpValue(const MachineInstr &MI,
+                               const MachineOperand &MO);
 
   public:
     static char ID;
@@ -55,7 +56,7 @@
     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
     /// machine instructions.
     ///
-    unsigned getBinaryCodeForInstr(MachineInstr &MI);
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
 
   private:
     void emitBasicBlock(MachineBasicBlock &MBB);
@@ -87,7 +88,7 @@
   MCE.StartMachineBasicBlock(&MBB);
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
        I != E; ++I) {
-    MachineInstr &MI = *I;
+    const MachineInstr &MI = *I;
     switch(MI.getOpcode()) {
     default:
       MCE.emitWordLE(getBinaryCodeForInstr(*I));
@@ -141,10 +142,11 @@
   }
 }
 
-int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+                                             const MachineOperand &MO) {
 
-  int rv = 0; // Return value; defaults to 0 for unhandled cases
-              // or things that get fixed up later by the JIT.
+  unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
+                   // or things that get fixed up later by the JIT.
 
   if (MO.isRegister()) {
     rv = getAlphaRegNumber(MO.getReg());

Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=55623&r1=55622&r2=55623&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue Sep  2 01:51:36 2008
@@ -38,7 +38,7 @@
     
     /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
     ///
-    int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+    unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
     
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<MachineModuleInfo>();
@@ -68,7 +68,7 @@
     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
     /// machine instructions.
     ///
-    unsigned getBinaryCodeForInstr(MachineInstr &MI);
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
   };
   char PPCCodeEmitter::ID = 0;
 }
@@ -100,10 +100,10 @@
   MCE.StartMachineBasicBlock(&MBB);
   
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
-    MachineInstr &MI = *I;
+    const MachineInstr &MI = *I;
     switch (MI.getOpcode()) {
     default:
-      MCE.emitWordBE(getBinaryCodeForInstr(*I));
+      MCE.emitWordBE(getBinaryCodeForInstr(MI));
       break;
     case TargetInstrInfo::DBG_LABEL:
     case TargetInstrInfo::EH_LABEL:
@@ -121,9 +121,10 @@
   }
 }
 
-int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+                                           const MachineOperand &MO) {
 
-  intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases
+  unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
                    // or things that get fixed up later by the JIT.
   if (MO.isRegister()) {
     rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());

Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=55623&r1=55622&r2=55623&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Tue Sep  2 01:51:36 2008
@@ -89,7 +89,7 @@
 
   // Emit function declaration
   o << "unsigned " << Target.getName() << "CodeEmitter::"
-    << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
+    << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
 
   // Emit instruction base values
   o << "  static const unsigned InstBits[] = {\n";
@@ -221,6 +221,7 @@
   o << "  const unsigned opcode = MI.getOpcode();\n"
     << "  unsigned Value = InstBits[opcode];\n"
     << "  unsigned op;\n"
+    << "  op = op;  // suppress warning\n"
     << "  switch (opcode) {\n";
 
   // Emit each case statement