[llvm-commits] [llvm] r55596 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td
Evan Cheng
evan.cheng at apple.com
Mon Sep 1 00:00:14 PDT 2008
Author: evancheng
Date: Mon Sep 1 02:00:14 2008
New Revision: 55596
URL: http://llvm.org/viewvc/llvm-project?rev=55596&view=rev
Log:
addrmode3 instruction encodings.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=55596&r1=55595&r2=55596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Sep 1 02:00:14 2008
@@ -155,7 +155,7 @@
class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
@@ -163,7 +163,7 @@
class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
@@ -173,7 +173,7 @@
class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
@@ -181,19 +181,18 @@
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: AI2<opcod, oops, iops, f, opc, asm, pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
-// Pre-indexed ops
-// loads
+// Pre-indexed loads
class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
@@ -202,18 +201,18 @@
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
-// stores
+// Pre-indexed stores
class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit
@@ -222,19 +221,18 @@
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit
}
-// Post-indexed ops
-// loads
+// Post-indexed loads
class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
@@ -243,18 +241,18 @@
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
- let Inst{20} = 1; // load bit
+ let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
}
-// stores
+// Post-indexed stores
class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit
@@ -263,7 +261,7 @@
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> {
- let Inst{20} = 0; // load bit
+ let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit
@@ -275,25 +273,193 @@
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>;
-// addrmode4 instructions
-class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+// loads
+class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
- : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
- asm, "", pattern>;
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 0; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 0; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+// stores
+class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 0; // W bit
+ let Inst{24} = 1; // P bit
+}
+
+// Pre-indexed loads
+class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+ asm, cstr, pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+ asm, cstr, pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 1; // P bit
+}
+class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
+ asm, cstr, pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 0; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 1; // P bit
+}
-// Pre-indexed ops
-class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+// Pre-indexed stores
+class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
- asm, cstr, pattern>;
+ asm, cstr, pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 1; // P bit
+}
+// Post-indexed loads
+class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+ asm, cstr,pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 0; // P bit
+}
+class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+ asm, cstr,pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 0; // P bit
+}
+class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
+ asm, cstr,pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 0; // H bit
+ let Inst{6} = 1; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 1; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 0; // P bit
+}
-// Post-indexed ops
-class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+// Post-indexed stores
+class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
- asm, cstr,pattern>;
+ asm, cstr,pattern> {
+ let Inst{4} = 1;
+ let Inst{5} = 1; // H bit
+ let Inst{6} = 0; // S bit
+ let Inst{7} = 1;
+ let Inst{20} = 0; // L bit
+ let Inst{21} = 1; // W bit
+ let Inst{24} = 0; // P bit
+}
+
+
+// addrmode4 instructions
+class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
+ string asm, list<dag> pattern>
+ : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
+ asm, "", pattern>;
+
// Special cases.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=55596&r1=55595&r2=55596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 1 02:00:14 2008
@@ -597,7 +597,7 @@
"ldr", " $dst, $addr", []>;
// Loads with zero extension
-def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
+def LDRH : AI3ldh<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
@@ -606,17 +606,17 @@
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
// Loads with sign extension
-def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
+def LDRSH : AI3ldsh<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
-def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
+def LDRSB : AI3ldsb<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1 in {
// Load doubleword
-def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
+def LDRD : AI3ldd<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "d $dst, $addr",
[]>, Requires<[IsARM, HasV5T]>;
@@ -629,11 +629,11 @@
(ins GPR:$base, am2offset:$offset), LdFrm,
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb),
+def LDRH_PRE : AI3ldhpr<0xB, (outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdFrm,
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb),
+def LDRH_POST : AI3ldhpo<0xB, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
@@ -645,19 +645,19 @@
(ins GPR:$base,am2offset:$offset), LdFrm,
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb),
+def LDRSH_PRE : AI3ldshpr<0xE, (outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdFrm,
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb),
+def LDRSH_POST: AI3ldshpo<0xE, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
+def LDRSB_PRE : AI3ldsbpr<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdFrm,
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
+def LDRSB_POST: AI3ldsbpo<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
}
@@ -668,7 +668,7 @@
[(store GPR:$src, addrmode2:$addr)]>;
// Stores with truncate
-def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
+def STRH : AI3sth<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
"str", "h $src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
@@ -678,7 +678,7 @@
// Store doubleword
let mayStore = 1 in
-def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
+def STRD : AI3std<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
"str", "d $src, $addr",
[]>, Requires<[IsARM, HasV5T]>;
@@ -695,13 +695,13 @@
[(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
-def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb),
+def STRH_PRE : AI3sthpr<0xB, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
"str", "h $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
-def STRH_POST: AI3po<0xB, (outs GPR:$base_wb),
+def STRH_POST: AI3sthpo<0xB, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
"str", "h $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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