[llvm-commits] [llvm] r55555 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp

[Owen Anderson]

Author: resistor
Date: Fri Aug 29 19:38:46 2008
New Revision: 55555

URL: http://llvm.org/viewvc/llvm-project?rev=55555&view=rev
Log:
Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=55555&r1=55554&r2=55555&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Fri Aug 29 19:38:46 2008
@@ -225,6 +225,9 @@
   
   bool SelectCast(Instruction *I, ISD::NodeType Opcode,
                   DenseMap<const Value*, unsigned> &ValueMap);
+                  
+  void UpdateValueMap(Instruction* I, unsigned Reg, 
+                      DenseMap<const Value*, unsigned> &ValueMap);
 };
 
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55555&r1=55554&r2=55555&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Aug 29 19:38:46 2008
@@ -63,6 +63,21 @@
   return Reg;
 }
 
+/// UpdateValueMap - Update the value map to include the new mapping for this
+/// instruction, or insert an extra copy to get the result in a previous
+/// determined register.
+/// NOTE: This is only necessary because we might select a block that uses
+/// a value before we select the block that defines the value.  It might be
+/// possible to fix this by selecting blocks in reverse postorder.
+void FastISel::UpdateValueMap(Instruction* I, unsigned Reg, 
+                              DenseMap<const Value*, unsigned> &ValueMap) {
+  if (!ValueMap.count(I))
+    ValueMap[I] = Reg;
+  else
+     TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
+                      Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
+}
+
 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 /// which has an opcode which directly corresponds to the given ISD opcode.
 ///
@@ -90,7 +105,7 @@
                                      ISDOpcode, Op0, CI->getZExtValue());
     if (ResultReg != 0) {
       // We successfully emitted code for the given LLVM Instruction.
-      ValueMap[I] = ResultReg;
+      UpdateValueMap(I, ResultReg, ValueMap);
       return true;
     }
   }
@@ -101,7 +116,7 @@
                                      ISDOpcode, Op0, CF);
     if (ResultReg != 0) {
       // We successfully emitted code for the given LLVM Instruction.
-      ValueMap[I] = ResultReg;
+      UpdateValueMap(I, ResultReg, ValueMap);
       return true;
     }
   }
@@ -120,7 +135,7 @@
     return false;
 
   // We successfully emitted code for the given LLVM Instruction.
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -196,7 +211,7 @@
   }
 
   // We successfully emitted code for the given LLVM Instruction.
-  ValueMap[I] = N;
+  UpdateValueMap(I, N, ValueMap);
   return true;
 }
 
@@ -223,7 +238,7 @@
   if (!ResultReg)
     return false;
     
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -234,7 +249,7 @@
     unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
     if (Reg == 0)
       return false;
-    ValueMap[I] = Reg;
+    UpdateValueMap(I, Reg, ValueMap);
     return true;
   }
 
@@ -274,7 +289,7 @@
   if (!ResultReg)
     return false;
   
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -384,7 +399,7 @@
       MVT DstVT = TLI.getValueType(I->getType());
       if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
         if (ValueMap[I->getOperand(0)]) {
-          ValueMap[I] = ValueMap[I->getOperand(0)];
+          UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
           break;
         } else
           // Unhandled operand