[llvm-commits] [llvm] r54801 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Dan Gohman]

Author: djg
Date: Thu Aug 14 17:43:26 2008
New Revision: 54801

URL: http://llvm.org/viewvc/llvm-project?rev=54801&view=rev
Log:
Don't try to use the insertps instruction for vector
element inserts with non-constant indices. This fixes
CodeGen/X86/vector-variable-idx.ll on machines that
have SSE4.1.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=54801&r1=54800&r2=54801&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug 14 17:43:26 2008
@@ -4153,7 +4153,7 @@
     if (N2.getValueType() != MVT::i32)
       N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
     return DAG.getNode(Opc, VT, N0, N1, N2);
-  } else if (EVT == MVT::f32) {
+  } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
     // Bits [7:6] of the constant are the source select.  This will always be
     //  zero here.  The DAG Combiner may combine an extract_elt index into these
     //  bits.  For example (insert (extract, 3), 2) could be matched by putting