[llvm-commits] [llvm] r54749 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Dan Gohman]

Author: djg
Date: Wed Aug 13 14:47:40 2008
New Revision: 54749

URL: http://llvm.org/viewvc/llvm-project?rev=54749&view=rev
Log:
Rename SelectionDAGISel's FastISel to Fast, to begin to make
room for the new FastISel instruction selection code.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=54749&r1=54748&r2=54749&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Wed Aug 13 14:47:40 2008
@@ -42,12 +42,12 @@
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   CollectorMetadata *GCI;
-  bool FastISel;
+  bool Fast;
   std::vector<SDNode*> TopOrder;
   static char ID;
 
   explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : 
-    FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {}
+    FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), Fast(fast), DAGSize(0) {}
   
   TargetLowering &getTargetLowering() { return TLI; }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=54749&r1=54748&r2=54749&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Aug 13 14:47:40 2008
@@ -5379,7 +5379,7 @@
 
   if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
   
-  if (!FastISel && EnableValueProp)
+  if (!Fast && EnableValueProp)
     ComputeLiveOutVRegInfo(DAG);
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -5448,7 +5448,7 @@
     BasicBlock *LLVMBB = &*I;
     PHINodesToUpdate.clear();
 
-    if (!FastISel || !SISel.SelectBasicBlock(LLVMBB,  FuncInfo.MBBMap[LLVMBB]))
+    if (!Fast || !SISel.SelectBasicBlock(LLVMBB,  FuncInfo.MBBMap[LLVMBB]))
       SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
     FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
   }
@@ -5696,7 +5696,7 @@
     RegisterScheduler::setDefault(Ctor);
   }
   
-  ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+  ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
   Scheduler->Run();
 
   return Scheduler;