[llvm-commits] [llvm] r53462 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeTypes.h LegalizeVectorTypes.cpp

[Duncan Sands]

Author: baldrick
Date: Fri Jul 11 12:02:09 2008
New Revision: 53462

URL: http://llvm.org/viewvc/llvm-project?rev=53462&view=rev
Log:
Remove an apparently useless routine: there should
be no need to split the result of a vector RET node,
since they are always already legal.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=53462&r1=53461&r2=53462&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jul 11 12:02:09 2008
@@ -440,7 +440,6 @@
   SDOperand SplitVecOp_BIT_CONVERT(SDNode *N);
   SDOperand SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
   SDOperand SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
-  SDOperand SplitVecOp_RET(SDNode *N, unsigned OpNo);
   SDOperand SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
   SDOperand SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=53462&r1=53461&r2=53462&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Jul 11 12:02:09 2008
@@ -547,7 +547,6 @@
       assert(0 && "Do not know how to split this operator's operand!");
       abort();
     case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
-    case ISD::RET:   Res = SplitVecOp_RET(N, OpNo); break;
 
     case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
 
@@ -604,19 +603,6 @@
   return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
 }
 
-SDOperand DAGTypeLegalizer::SplitVecOp_RET(SDNode *N, unsigned OpNo) {
-  assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
-  // FIXME: Returns of gcc generic vectors larger than a legal vector
-  // type should be returned by reference!
-  SDOperand Lo, Hi;
-  GetSplitVector(N->getOperand(1), Lo, Hi);
-
-  SDOperand Chain = N->getOperand(0);  // The chain.
-  SDOperand Sign = N->getOperand(2);  // Signness
-
-  return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
-}
-
 SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
   // For example, i64 = BIT_CONVERT v4i16 on alpha.  Typically the vector will
   // end up being split all the way down to individual components.  Convert the