[llvm-commits] [llvm] r53421 - in /llvm/branches/Apple/Gaz: include/llvm/CodeGen/LiveIntervalAnalysis.h include/llvm/CodeGen/MachineInstr.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/MachineInstr.cpp lib/CodeGen/RegAllocLocal.cpp lib/CodeGen/RegAllocSimple.cpp
Bill Wendling
isanbard at gmail.com
Thu Jul 10 14:06:01 PDT 2008
Author: void
Date: Thu Jul 10 16:06:00 2008
New Revision: 53421
URL: http://llvm.org/viewvc/llvm-project?rev=53421&view=rev
Log:
Pull r53344, r53346, r53351, r53352, r53389, r53390, r53394 into Gaz.
Modified:
llvm/branches/Apple/Gaz/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/branches/Apple/Gaz/include/llvm/CodeGen/MachineInstr.h
llvm/branches/Apple/Gaz/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/Apple/Gaz/lib/CodeGen/MachineInstr.cpp
llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocLocal.cpp
llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocSimple.cpp
Modified: llvm/branches/Apple/Gaz/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/branches/Apple/Gaz/include/llvm/CodeGen/LiveIntervalAnalysis.h Thu Jul 10 16:06:00 2008
@@ -328,14 +328,14 @@
/// handleVirtualRegisterDef)
void handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI, unsigned MIIdx,
- MachineOperand& MO);
+ MachineOperand& MO, unsigned MOIdx);
/// handleVirtualRegisterDef - update intervals for a virtual
/// register def
void handleVirtualRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
unsigned MIIdx, MachineOperand& MO,
- LiveInterval& interval);
+ unsigned MOIdx, LiveInterval& interval);
/// handlePhysicalRegisterDef - update intervals for a physical register
/// def.
Modified: llvm/branches/Apple/Gaz/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/include/llvm/CodeGen/MachineInstr.h?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/branches/Apple/Gaz/include/llvm/CodeGen/MachineInstr.h Thu Jul 10 16:06:00 2008
@@ -207,9 +207,9 @@
/// none is found.
int findFirstPredOperandIdx() const;
- /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
- /// to two addr elimination.
- bool isRegReDefinedByTwoAddr(unsigned Reg) const;
+ /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+ /// check if the register def is a re-definition due to two addr elimination.
+ bool isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const;
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
Modified: llvm/branches/Apple/Gaz/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/Apple/Gaz/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jul 10 16:06:00 2008
@@ -298,6 +298,7 @@
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
unsigned MIIdx, MachineOperand& MO,
+ unsigned MOIdx,
LiveInterval &interval) {
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
@@ -390,7 +391,7 @@
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(interval.reg)) {
+ if (mi->isRegReDefinedByTwoAddr(interval.reg, MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
@@ -553,9 +554,10 @@
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
unsigned MIIdx,
- MachineOperand& MO) {
+ MachineOperand& MO,
+ unsigned MOIdx) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
- handleVirtualRegisterDef(MBB, MI, MIIdx, MO,
+ handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
getOrCreateInterval(MO.getReg()));
else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
@@ -660,7 +662,7 @@
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
if (MO.isRegister() && MO.getReg() && MO.isDef())
- handleRegisterDef(MBB, MI, MIIndex, MO);
+ handleRegisterDef(MBB, MI, MIIndex, MO, i);
}
MIIndex += InstrSlots::NUM;
Modified: llvm/branches/Apple/Gaz/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/lib/CodeGen/MachineInstr.cpp?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/Apple/Gaz/lib/CodeGen/MachineInstr.cpp Thu Jul 10 16:06:00 2008
@@ -623,20 +623,15 @@
return -1;
}
-/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
-/// to two addr elimination.
-bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
+/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+/// check if the register def is a re-definition due to two addr elimination.
+bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
const TargetInstrDesc &TID = getDesc();
- for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
- const MachineOperand &MO1 = getOperand(i);
- if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
- for (unsigned j = i+1; j < e; ++j) {
- const MachineOperand &MO2 = getOperand(j);
- if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
- TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
- return true;
- }
- }
+ for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = getOperand(i);
+ if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
+ TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
+ return true;
}
return false;
}
Modified: llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocLocal.cpp?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocLocal.cpp Thu Jul 10 16:06:00 2008
@@ -25,6 +25,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
@@ -239,6 +240,9 @@
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum);
+ /// ComputeLocalLiveness - Computes liveness of registers within a basic
+ /// block, setting the killed/dead flags as appropriate.
+ void ComputeLocalLiveness(MachineBasicBlock& MBB);
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg);
@@ -250,9 +254,9 @@
/// to be held on the stack.
int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
// Find the location Reg would belong...
- std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
- if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
+ if (I != StackSlotForVirtReg.end())
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
@@ -291,8 +295,6 @@
DOUT << " Spilling register " << TRI->getName(PhysReg)
<< " containing %reg" << VirtReg;
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
-
if (!isVirtRegModified(VirtReg)) {
DOUT << " which has not been modified, so no store necessary!";
std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
@@ -507,7 +509,6 @@
<< TRI->getName(PhysReg) << "\n";
// Add move instruction(s)
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
@@ -561,39 +562,25 @@
return false;
}
-void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
- // loop over each instruction
- MachineBasicBlock::iterator MII = MBB.begin();
- const TargetInstrInfo &TII = *TM->getInstrInfo();
-
- DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
- if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
+namespace llvm {
+ template<> struct DenseMapInfo<uint32_t> {
+ static inline uint32_t getEmptyKey() { return ~0; }
+ static inline uint32_t getTombstoneKey() { return ~0 - 1; }
+ static unsigned getHashValue(const uint32_t& Val) { return Val * 37; }
+ static bool isPod() { return true; }
+ static bool isEqual(const uint32_t& LHS, const uint32_t& RHS) {
+ return LHS == RHS;
+ }
+ };
+}
- // If this is the first basic block in the machine function, add live-in
- // registers as active.
- if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
- for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
- E = MBB.livein_end(); I != E; ++I) {
- unsigned Reg = *I;
- MF->getRegInfo().setPhysRegUsed(Reg);
- PhysRegsUsed[Reg] = 0; // It is free and reserved now
- AddToPhysRegsUseOrder(Reg);
- for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
- *AliasSet; ++AliasSet) {
- if (PhysRegsUsed[*AliasSet] != -2) {
- AddToPhysRegsUseOrder(*AliasSet);
- PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- MF->getRegInfo().setPhysRegUsed(*AliasSet);
- }
- }
- }
- }
-
-
+/// ComputeLocalLiveness - Computes liveness of registers within a basic
+/// block, setting the killed/dead flags as appropriate.
+void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
// Keep track of the most recently seen previous use or def of each reg,
// so that we can update them with dead/kill markers.
- std::map<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
+ DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
@@ -612,26 +599,20 @@
// - A def followed by a def is dead
// - A use followed by a def is a kill
if (MO.isReg() && MO.getReg() && MO.isDef()) {
- std::map<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
+ DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
last = LastUseDef.find(MO.getReg());
if (last != LastUseDef.end()) {
-
- // If this is a two address instr, then we don't mark the def
- // as killing the use.
+ // Check if this is a two address instruction. If so, then
+ // the def does not kill the use.
if (last->second.first == I &&
- I->getDesc().getOperandConstraint(last->second.second,
- TOI::TIED_TO) == (signed)i) {
- LastUseDef[MO.getReg()] = std::make_pair(I, i);
+ I->isRegReDefinedByTwoAddr(MO.getReg(), i))
continue;
- }
-
MachineOperand& lastUD =
last->second.first->getOperand(last->second.second);
-
if (lastUD.isDef())
lastUD.setIsDead(true);
- else if (lastUD.isUse())
+ else
lastUD.setIsKill(true);
}
@@ -655,7 +636,7 @@
// Finally, loop over the final use/def of each reg
// in the block and determine if it is dead.
- for (std::map<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
+ for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
MachineInstr* MI = I->second.first;
unsigned idx = I->second.second;
@@ -686,10 +667,40 @@
if (isPhysReg || !usedOutsideBlock) {
if (MO.isUse())
MO.setIsKill(true);
- else if (MI->getOperand(idx).isDef())
+ else
MO.setIsDead(true);
}
}
+}
+
+void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
+ // loop over each instruction
+ MachineBasicBlock::iterator MII = MBB.begin();
+
+ DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
+ if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
+
+ // If this is the first basic block in the machine function, add live-in
+ // registers as active.
+ if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
+ for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
+ E = MBB.livein_end(); I != E; ++I) {
+ unsigned Reg = *I;
+ MF->getRegInfo().setPhysRegUsed(Reg);
+ PhysRegsUsed[Reg] = 0; // It is free and reserved now
+ AddToPhysRegsUseOrder(Reg);
+ for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
+ *AliasSet; ++AliasSet) {
+ if (PhysRegsUsed[*AliasSet] != -2) {
+ AddToPhysRegsUseOrder(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ MF->getRegInfo().setPhysRegUsed(*AliasSet);
+ }
+ }
+ }
+ }
+
+ ComputeLocalLiveness(MBB);
// Otherwise, sequentially allocate each instruction in the MBB.
while (MII != MBB.end()) {
@@ -854,7 +865,7 @@
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
DOUT << " Assigning " << TRI->getName(DestPhysReg)
<< " to %reg" << DestVirtReg << "\n";
- MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
+ MO.setReg(DestPhysReg); // Assign the output register
}
}
@@ -893,7 +904,7 @@
// Finally, if this is a noop copy instruction, zap it.
unsigned SrcReg, DstReg;
- if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
+ if (TII->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
MBB.erase(MI);
}
Modified: llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocSimple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocSimple.cpp?rev=53421&r1=53420&r2=53421&view=diff
==============================================================================
--- llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocSimple.cpp (original)
+++ llvm/branches/Apple/Gaz/lib/CodeGen/RegAllocSimple.cpp Thu Jul 10 16:06:00 2008
@@ -103,10 +103,9 @@
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
- std::map<unsigned, int>::iterator I =
- StackSlotForVirtReg.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
- if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
+ if (I != StackSlotForVirtReg.end())
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
@@ -190,12 +189,12 @@
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand &op = MI->getOperand(i);
+ MachineOperand &MO = MI->getOperand(i);
- if (op.isRegister() && op.getReg() &&
- TargetRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtualReg = (unsigned) op.getReg();
- DOUT << "op: " << op << "\n";
+ if (MO.isRegister() && MO.getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned virtualReg = (unsigned) MO.getReg();
+ DOUT << "op: " << MO << "\n";
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
@@ -203,7 +202,7 @@
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.isDef()) {
+ if (MO.isDef()) {
int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
@@ -224,8 +223,8 @@
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- MI->getOperand(i).setReg(physReg);
- DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
+ MO.setReg(physReg);
+ DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
}
}
RegClassIdx.clear();
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