[llvm-commits] [llvm] r53277 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsISelLowering.cpp MipsInstrInfo.td MipsSubtarget.cpp MipsSubtarget.h
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Tue Jul 8 22:32:23 PDT 2008
Author: bruno
Date: Wed Jul 9 00:32:22 2008
New Revision: 53277
URL: http://llvm.org/viewvc/llvm-project?rev=53277&view=rev
Log:
Fixed features usage.
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=53277&r1=53276&r2=53277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Wed Jul 9 00:32:22 2008
@@ -33,20 +33,22 @@
// Mips Subtarget features //
//===----------------------------------------------------------------------===//
-def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
+def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
-def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
+def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">;
-def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
+def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">;
-def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU",
- "true", "Enable Allegrex VFPU instructions.">;
-def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
+def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
-def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
+def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
"Enable o32 ABI">;
-def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
+def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
"Enable eabi ABI">;
+def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
+ "true", "Enable vector FPU instructions.">;
+def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
+ "Enable 'signext in register' instructions.">;
//===----------------------------------------------------------------------===//
// Mips processors supported.
@@ -64,8 +66,8 @@
// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
// but much more similar to Mips2 than Mips3.
-def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU,
- FeatureEABI]>;
+def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
+ FeatureSEInReg, FeatureVFPU]>;
def Mips : Target {
let InstructionSet = MipsInstrInfo;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=53277&r1=53276&r2=53277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jul 9 00:32:22 2008
@@ -122,7 +122,7 @@
if (Subtarget->isSingleFloat())
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
- if (!Subtarget->isAllegrex()) {
+ if (!Subtarget->hasSEInReg()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=53277&r1=53276&r2=53277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Jul 9 00:32:22 2008
@@ -50,7 +50,7 @@
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
-def IsAllegrex : Predicate<"Subtarget.isAllegrex()">;
+def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@@ -510,7 +510,7 @@
//def MSUB : MArithR<0x04, "msub">;
//def MSUBU : MArithR<0x05, "msubu">;
-let Predicates = [IsAllegrex] in {
+let Predicates = [HasSEInReg] in {
let shamt = 0x10, rs = 0 in
def SEB : SignExtInReg<0x21, "seb", i8>;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=53277&r1=53276&r2=53277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Wed Jul 9 00:32:22 2008
@@ -20,7 +20,7 @@
MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
const std::string &FS, bool little) :
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
- IsFP64bit(false), IsGP64bit(false), HasAllegrexVFPU(false), IsAllegrex(false)
+ IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false)
{
std::string CPU = "mips1";
@@ -36,7 +36,7 @@
MipsABI = EABI;
IsSingleFloat = true;
MipsArchVersion = Mips2;
- HasAllegrexVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
- IsAllegrex = true;
+ HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
+ HasSEInReg = true;
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=53277&r1=53276&r2=53277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Wed Jul 9 00:32:22 2008
@@ -27,7 +27,7 @@
protected:
enum MipsArchEnum {
- Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
+ Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
};
enum MipsABIEnum {
@@ -54,11 +54,11 @@
// IsFP64bit - General-purpose registers are 64 bits wide
bool IsGP64bit;
- // HasAllegrexVFPU - Allegrex processor has a vector floating point unit.
- bool HasAllegrexVFPU;
+ // HasVFPU - Processor has a vector floating point unit.
+ bool HasVFPU;
- // IsAllegrex - The target processor is a Allegrex core.
- bool IsAllegrex;
+ // HasSEInReg - Target has SEB and SEH (signext in register) instructions.
+ bool HasSEInReg;
InstrItineraryData InstrItins;
@@ -85,8 +85,8 @@
bool isGP32bit() const { return !IsGP64bit; };
bool isSingleFloat() const { return IsSingleFloat; };
bool isNotSingleFloat() const { return !IsSingleFloat; };
- bool hasAllegrexVFPU() const { return HasAllegrexVFPU; };
- bool isAllegrex() const { return IsAllegrex; };
+ bool hasVFPU() const { return HasVFPU; };
+ bool hasSEInReg() const { return HasSEInReg; };
};
} // End llvm namespace
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