[llvm-commits] [llvm] r52691 - in /llvm/trunk/lib/Target/X86: X86CallingConv.td X86ISelLowering.cpp X86InstrMMX.td X86RegisterInfo.td
Dale Johannesen
dalej at apple.com
Tue Jun 24 15:45:28 PDT 2008
On Jun 24, 2008, at 3:32 PMPDT, Chris Lattner wrote:
>
> On Jun 24, 2008, at 3:01 PM, Dale Johannesen wrote:
>
>> Author: johannes
>> Date: Tue Jun 24 17:01:44 2008
>> New Revision: 52691
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=52691&view=rev
>> Log:
>> Add v2f32 (MMX) type to X86. Support is primitive:
>> load,store,call,return,bitcast. This is enough to
>> make call and return work.
>
> If LLVM IR contains an add (or some other operation) on v2f32 values,
> do they correctly still get scalarized?
>
> -Chris
I haven't tested extensively, but add of two v2f32's appears to
produce the right
code (two float adds).
>> Modified:
>> llvm/trunk/lib/Target/X86/X86CallingConv.td
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> llvm/trunk/lib/Target/X86/X86InstrMMX.td
>> llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>>
>> Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=52691&r1=52690&r2=52691&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86CallingConv.td Tue Jun 24 17:01:44
>> 2008
>> @@ -35,7 +35,7 @@
>>
>> // MMX vector types are always returned in MM0. If the target
>> doesn't have
>> // MM0, it doesn't support these vector types.
>> - CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[MM0]>>,
>> + CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
>> CCAssignToReg<[MM0]>>,
>>
>> // Long double types are always returned in ST0 (even with SSE).
>> CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
>> @@ -75,6 +75,9 @@
>> // The X86-64 calling convention always returns FP values in XMM0.
>> CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
>> CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
>> +
>> + // MMX vector types are always returned in XMM0.
>> + CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0,
>> XMM1]>>,
>> CCDelegateTo<RetCC_X86Common>
>> ]>;
>>
>> @@ -141,7 +144,7 @@
>>
>> // The first 8 MMX (except for v1i64) vector arguments are passed
>> in XMM
>> // registers on Darwin.
>> - CCIfType<[v8i8, v4i16, v2i32],
>> + CCIfType<[v8i8, v4i16, v2i32, v2f32],
>> CCIfSubtarget<"isTargetDarwin()",
>> CCIfSubtarget<"hasSSE2()",
>> CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6,
>> XMM7]>>>>,
>> @@ -163,7 +166,7 @@
>> CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
>> CCAssignToStack<16, 16>>,
>>
>> // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
>> - CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
>> + CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8,
>> 8>>
>> ]>;
>>
>> // Calling convention used on Win64
>> @@ -189,7 +192,7 @@
>> [RCX , RDX , R8 , R9 ]>>,
>>
>> // The first 4 MMX vector arguments are passed in GPRs.
>> - CCIfType<[v8i8, v4i16, v2i32, v1i64],
>> + CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
>> CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
>> [XMM0, XMM1, XMM2, XMM3]>>,
>>
>> @@ -230,7 +233,7 @@
>>
>> // The first 8 MMX (except for v1i64) vector arguments are passed
>> in XMM
>> // registers on Darwin.
>> - CCIfType<[v8i8, v4i16, v2i32],
>> + CCIfType<[v8i8, v4i16, v2i32, v2f32],
>> CCIfSubtarget<"isTargetDarwin()",
>> CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6,
>> XMM7]>>>,
>>
>> @@ -270,7 +273,7 @@
>>
>> // The first 3 __m64 (except for v1i64) vector arguments are
>> passed in mmx
>> // registers if the call is not a vararg call.
>> - CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32],
>> + CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
>> CCAssignToReg<[MM0, MM1, MM2]>>>,
>>
>> // Integer/Float values get stored in stack slots that are 4 bytes
>> in
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=52691&r1=52690&r2=52691&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 24
>> 17:01:44 2008
>> @@ -536,6 +536,7 @@
>> addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
>> addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
>> addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
>> + addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
>> addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
>>
>> // FIXME: add MMX packed arithmetics
>> @@ -583,11 +584,14 @@
>> AddPromotedToType (ISD::LOAD, MVT::v4i16,
>> MVT::v1i64);
>> setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
>> AddPromotedToType (ISD::LOAD, MVT::v2i32,
>> MVT::v1i64);
>> + setOperationAction(ISD::LOAD, MVT::v2f32,
>> Promote);
>> + AddPromotedToType (ISD::LOAD, MVT::v2f32,
>> MVT::v1i64);
>> setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
>>
>> setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
>> setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
>> setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
>> + setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
>> setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
>>
>> setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
>> @@ -894,7 +898,7 @@
>> // Don't emit a copytoreg.
>> continue;
>> }
>> -
>> +
>> Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
>> Flag = Chain.getValue(1);
>> }
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=52691&r1=52690&r2=52691&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Jun 24 17:01:44 2008
>> @@ -528,20 +528,30 @@
>> (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
>> def : Pat<(store (v2i32 VR64:$src), addr:$dst),
>> (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
>> +def : Pat<(store (v2f32 VR64:$src), addr:$dst),
>> + (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
>> def : Pat<(store (v1i64 VR64:$src), addr:$dst),
>> (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
>>
>> // Bit convert.
>> def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
>> def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
>> +def : Pat<(v8i8 (bitconvert (v2f32 VR64:$src))), (v8i8
>> VR64:$src)>;
>> def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
>> def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
>> def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
>> +def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16
>> VR64:$src)>;
>> def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
>> def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
>> +def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32
>> VR64:$src)>;
>> def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
>> def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
>> +def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32
>> VR64:$src)>;
>> +def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32
>> VR64:$src)>;
>> +def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32
>> VR64:$src)>;
>> +def : Pat<(v2f32 (bitconvert (v8i8 VR64:$src))), (v2f32
>> VR64:$src)>;
>> def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
>> +def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64
>> VR64:$src)>;
>> def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
>> def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
>>
>> @@ -550,6 +560,8 @@
>> (MMX_MOVD64to64rr GR64:$src)>;
>> def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
>> (MMX_MOVD64to64rr GR64:$src)>;
>> +def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
>> + (MMX_MOVD64to64rr GR64:$src)>;
>> def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
>> (MMX_MOVD64to64rr GR64:$src)>;
>> def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
>> @@ -558,6 +570,8 @@
>> (MMX_MOVD64from64rr VR64:$src)>;
>> def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
>> (MMX_MOVD64from64rr VR64:$src)>;
>> +def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
>> + (MMX_MOVD64from64rr VR64:$src)>;
>> def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
>> (MMX_MOVD64from64rr VR64:$src)>;
>> def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
>>
>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=52691&r1=52690&r2=52691&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Jun 24 17:01:44
>> 2008
>> @@ -509,7 +509,7 @@
>> }
>>
>> // Generic vector registers: VR64 and VR128.
>> -def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
>> +def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64,
>> v2f32], 64,
>> [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
>> def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32,
>> v2f64],128,
>> [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6,
>> XMM7,
>>
>>
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