[llvm-commits] [llvm] r51877 - in /llvm/trunk: test/CodeGen/X86/variadic-node-pic.ll utils/TableGen/DAGISelEmitter.cpp

[Dan Gohman]

Author: djg
Date: Mon Jun  2 12:40:38 2008
New Revision: 51877

URL: http://llvm.org/viewvc/llvm-project?rev=51877&view=rev
Log:
Fix the position of MemOperands in nodes that use variadic_ops
in DAGISelEmitter output. This bug was recently uncovered by the
addition of patterns for CALL32m and CALL64m, which are nodes
that now have both MemOperands and variadic_ops.

This bug was especially visible with PIC in various configurations,
because the new patterns are matching the indirect call code used
in many PIC configurations.

Added:
    llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll
Modified:
    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp

Added: llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll?rev=51877&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll (added)
+++ llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll Mon Jun  2 12:40:38 2008
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -relocation-model=pic -code-model=large
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+declare void @xscanf(i64) nounwind 
+
+define void @foo() nounwind  {
+	call void (i64)* @xscanf( i64 0 ) nounwind
+	unreachable
+}

Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=51877&r1=51876&r2=51877&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun  2 12:40:38 2008
@@ -992,18 +992,6 @@
         }
       }
 
-      // Generate MemOperandSDNodes nodes for each memory accesses covered by 
-      // this pattern.
-      if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
-        std::vector<std::string>::const_iterator mi, mie;
-        for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
-          emitCode("SDOperand LSI_" + *mi + " = "
-                   "CurDAG->getMemOperand(cast<LSBaseSDNode>(" +
-                   *mi + ")->getMemOperand());");
-          AllOps.push_back("LSI_" + *mi);
-        }
-      }
-
       // Emit all the chain and CopyToReg stuff.
       bool ChainEmitted = NodeHasChain;
       if (NodeHasChain)
@@ -1088,6 +1076,21 @@
           emitCode("}");
         }
 
+        // Generate MemOperandSDNodes nodes for each memory accesses covered by 
+        // this pattern.
+        if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
+          std::vector<std::string>::const_iterator mi, mie;
+          for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
+            emitCode("SDOperand LSI_" + *mi + " = "
+                     "CurDAG->getMemOperand(cast<LSBaseSDNode>(" +
+                     *mi + ")->getMemOperand());");
+            if (IsVariadic)
+              emitCode("Ops" + utostr(OpsNo) + ".push_back(LSI_" + *mi + ");");
+            else
+              AllOps.push_back("LSI_" + *mi);
+          }
+        }
+
         if (NodeHasChain) {
           if (IsVariadic)
             emitCode("Ops" + utostr(OpsNo) + ".push_back(" + ChainName + ");");