[llvm-commits] [llvm] r51140 - in /llvm/trunk: include/llvm/CodeGen/MachineFrameInfo.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h

[Chris Lattner]

Hi Evan,

On May 15, 2008, at 1:39 AM, Evan Cheng wrote:

> /// getZeroVector - Returns a vector of specified type with all zero  
> elements.
> ///
> -static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG  
> &DAG) {
> +static SDOperand getZeroVector(MVT::ValueType VT, bool HasSSE2,
> +                               SelectionDAG &DAG) {
>   assert(MVT::isVector(VT) && "Expected a vector type");
>
>   // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted  
> to their dest
>   // type.  This ensures they get CSE'd.
> -  SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
>   SDOperand Vec;
> -  if (MVT::getSizeInBits(VT) == 64)  // MMX
> +  if (MVT::getSizeInBits(VT) == 64) { // MMX
> +    SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
>     Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
> -  else                                              // SSE
> +  } else if (HasSSE2) {  // SSE2
> +    SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
>     Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst,  
> Cst);
> +  } else { // SSE1
> +    SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
> +    Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst,  
> Cst);
> +  }
>   return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
> }

Why does this build a different vector type depending on whether SSE2  
is available or not?  Why not always make the v4f32 version?

-Chris