[llvm-commits] [llvm] r50838 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrMMX.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_set-5.ll test/CodeGen/X86/vec_set-6.ll test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_set-D.ll

[Evan Cheng]

That's a different bug. :-) But yes, I want to see if that's possible.

Evan

On May 7, 2008, at 6:07 PM, Chris Lattner wrote:

> On May 7, 2008, at 5:57 PM, Evan Cheng wrote:
>> URL: http://llvm.org/viewvc/llvm-project?rev=50838&view=rev
>> Log:
>> Handle vector move / load which zero the destination register top
>> bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific
>> dag combine.
>
> Very nice, the testcase improvements are very cool.
>
> I notice that vec_set-C on x86-32 compiles into:
>
> _t1:
> 	subl	$28, %esp
> 	movl	36(%esp), %eax
> 	movl	%eax, 4(%esp)
> 	movl	32(%esp), %eax
> 	movl	%eax, (%esp)
> 	movq	(%esp), %xmm0
> 	addl	$28, %esp
> 	ret
>
> Could this just compile to a movsd or movq [mem] -> xmm0?
>
> -Chris
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits