[llvm-commits] [llvm] r49832 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2008-04-16-CoalescerBug.ll

[Evan Cheng]

Author: evancheng
Date: Wed Apr 16 19:06:42 2008
New Revision: 49832

URL: http://llvm.org/viewvc/llvm-project?rev=49832&view=rev
Log:
Fix a sub-register indice propagation bug.

Added:
    llvm/trunk/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=49832&r1=49831&r2=49832&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Apr 16 19:06:42 2008
@@ -457,15 +457,14 @@
     MachineOperand &O = I.getOperand();
     MachineInstr *UseMI = &*I;
     ++I;
+    unsigned OldSubIdx = O.getSubReg();
     if (DstIsPhys) {
-      unsigned UseSubIdx = O.getSubReg();
       unsigned UseDstReg = DstReg;
-      if (UseSubIdx)
-        UseDstReg = tri_->getSubReg(DstReg, UseSubIdx);
+      if (OldSubIdx)
+          UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
       O.setReg(UseDstReg);
       O.setSubReg(0);
     } else {
-      unsigned OldSubIdx = O.getSubReg();
       // Sub-register indexes goes from small to large. e.g.
       // RAX: 0 -> AL, 1 -> AH, 2 -> AX, 3 -> EAX
       // EAX: 0 -> AL, 1 -> AH, 2 -> AX
@@ -849,10 +848,20 @@
     if (SrcIsPhys && isExtSubReg) {
       // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
       // coalesced with AX.
-      SrcReg = tri_->getSubReg(SrcReg, SubIdx);
+      unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
+      assert(!DstSubIdx || DstSubIdx == SubIdx);
+      if (DstSubIdx != SubIdx)
+        // r1024<2> = EXTRACT_SUBREG EAX, 0. Then r1024 has already been
+        // coalesced to an INSERT_SUBREG so the subreg indices cancel out.
+        SrcReg = tri_->getSubReg(SrcReg, SubIdx);
       SubIdx = 0;
     } else if (DstIsPhys && isInsSubReg) {
       // EAX = INSERT_SUBREG EAX, r1024, 0
+      unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
+      assert(!SrcSubIdx || SrcSubIdx == SubIdx);
+      if (SrcSubIdx != SubIdx)
+        // EAX = INSERT_SUBREG EAX, r1024<2>, 0 Then r1024 has already been
+        // coalesced to an EXTRACT_SUBREG so the subreg indices cancel out.
       DstReg = tri_->getSubReg(DstReg, SubIdx);
       SubIdx = 0;
     } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {

Added: llvm/trunk/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-16-CoalescerBug.ll?rev=49832&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-04-16-CoalescerBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-04-16-CoalescerBug.ll Wed Apr 16 19:06:42 2008
@@ -0,0 +1,33 @@
+; RUN: llvm-as < %s | llc -march=x86
+
+define void @Hubba(i8* %saveunder, i32 %firstBlob, i32 %select) nounwind  {
+entry:
+	br i1 false, label %bb53.us, label %bb53
+bb53.us:		; preds = %bb94.us, %bb53.us, %entry
+	switch i8 1, label %bb71.us [
+		 i8 0, label %bb53.us
+		 i8 1, label %bb94.us
+	]
+bb94.us:		; preds = %bb71.us, %bb53.us
+	%result.0.us = phi i32 [ %tmp93.us, %bb71.us ], [ 0, %bb53.us ]		; <i32> [#uses=2]
+	%tmp101.us = lshr i32 %result.0.us, 3		; <i32> [#uses=1]
+	%result.0163.us = trunc i32 %result.0.us to i16		; <i16> [#uses=2]
+	shl i16 %result.0163.us, 7		; <i16>:0 [#uses=1]
+	%tmp106.us = and i16 %0, -1024		; <i16> [#uses=1]
+	shl i16 %result.0163.us, 2		; <i16>:1 [#uses=1]
+	%tmp109.us = and i16 %1, -32		; <i16> [#uses=1]
+	%tmp111112.us = trunc i32 %tmp101.us to i16		; <i16> [#uses=1]
+	%tmp110.us = or i16 %tmp109.us, %tmp111112.us		; <i16> [#uses=1]
+	%tmp113.us = or i16 %tmp110.us, %tmp106.us		; <i16> [#uses=1]
+	store i16 %tmp113.us, i16* null, align 2
+	br label %bb53.us
+bb71.us:		; preds = %bb53.us
+	%tmp80.us = load i8* null, align 1		; <i8> [#uses=1]
+	%tmp8081.us = zext i8 %tmp80.us to i32		; <i32> [#uses=1]
+	%tmp87.us = mul i32 %tmp8081.us, 0		; <i32> [#uses=1]
+	%tmp92.us = add i32 0, %tmp87.us		; <i32> [#uses=1]
+	%tmp93.us = udiv i32 %tmp92.us, 255		; <i32> [#uses=1]
+	br label %bb94.us
+bb53:		; preds = %entry
+	ret void
+}