[llvm-commits] [llvm] r48815 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Evan Cheng]

Author: evancheng
Date: Wed Mar 26 03:11:49 2008
New Revision: 48815

URL: http://llvm.org/viewvc/llvm-project?rev=48815&view=rev
Log:
Fix some SSE4.1 instruction encoding bugs.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=48815&r1=48814&r2=48815&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 26 03:11:49 2008
@@ -3327,7 +3327,7 @@
 
 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
-  def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst),
+  def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
                  (ins VR128:$src1, i32i8imm:$src2),
                  !strconcat(OpcodeStr, 
                   "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -3363,7 +3363,7 @@
 
 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
-  def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst),
+  def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
                  (ins VR128:$src1, i32i8imm:$src2),
                  !strconcat(OpcodeStr, 
                   "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -3384,7 +3384,7 @@
 /// destination
 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
   // Not worth matching to rr form of extractps since the result is in GPR32.
-  def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst),
+  def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
                  (ins VR128:$src1, i32i8imm:$src2),
                  !strconcat(OpcodeStr, 
                   "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -3460,7 +3460,7 @@
   }
 }
 
-defm INSERTPS    : SS41I_insertf32<0x31, "insertps">;
+defm INSERTPS    : SS41I_insertf32<0x21, "insertps">;
 
 let Defs = [EFLAGS] in {
 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),