[llvm-commits] [llvm] r48627 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrMMX.td lib/VMCore/AutoUpgrade.cpp test/CodeGen/X86/mmx-shift.ll
Evan Cheng
evan.cheng at apple.com
Thu Mar 20 17:40:09 PDT 2008
Author: evancheng
Date: Thu Mar 20 19:40:09 2008
New Revision: 48627
URL: http://llvm.org/viewvc/llvm-project?rev=48627&view=rev
Log:
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
Modified:
llvm/trunk/include/llvm/IntrinsicsX86.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/VMCore/AutoUpgrade.cpp
llvm/trunk/test/CodeGen/X86/mmx-shift.ll
Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=48627&r1=48626&r2=48627&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu Mar 20 19:40:09 2008
@@ -916,53 +916,29 @@
def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">,
- Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">,
- Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">,
- Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">,
- Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">,
- Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">,
- Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">,
- Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
- llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>;
- def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">,
- Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
- llvm_i32_ty], [IntrNoMem]>;
}
// Pack ops.
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=48627&r1=48626&r2=48627&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Thu Mar 20 19:40:09 2008
@@ -104,30 +104,38 @@
//
multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> {
- def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
+ (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
- def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
+ (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst,
(OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
}
multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
- string OpcodeStr, Intrinsic IntId,
- Intrinsic ImmIntId> {
- def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
+ string OpcodeStr, Intrinsic IntId> {
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
+ (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
- def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
+ (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>;
- def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
+ def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
+ (ins VR64:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR64:$dst, (ImmIntId VR64:$src1, imm:$src2))]>;
+ [(set VR64:$dst, (IntId VR64:$src1,
+ (v1i64 (bitconvert
+ (v2i32 (vector_shuffle immAllZerosV,
+ (v2i32 (scalar_to_vector (i32 imm:$src2))),
+ MMX_MOVL_shuffle_mask))))))]>;
}
}
@@ -268,23 +276,23 @@
// Shift Instructions
defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
- int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
+ int_x86_mmx_psrl_w>;
defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
- int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
+ int_x86_mmx_psrl_d>;
defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
- int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
+ int_x86_mmx_psrl_q>;
defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
- int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
+ int_x86_mmx_psll_w>;
defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
- int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
+ int_x86_mmx_psll_d>;
defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
- int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
+ int_x86_mmx_psll_q>;
defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
- int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
+ int_x86_mmx_psra_w>;
defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
- int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
+ int_x86_mmx_psra_d>;
// Comparison Instructions
defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=48627&r1=48626&r2=48627&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Thu Mar 20 19:40:09 2008
@@ -122,8 +122,7 @@
if (Name.compare(5,10,"x86.mmx.ps",10) == 0 &&
(Name.compare(13,4,"psll", 4) == 0 ||
Name.compare(13,4,"psra", 4) == 0 ||
- Name.compare(13,4,"psrl", 4) == 0) &&
- Name[17] != 'i') {
+ Name.compare(13,4,"psrl", 4) == 0)) {
const llvm::Type *VT = VectorType::get(IntegerType::get(64), 1);
Modified: llvm/trunk/test/CodeGen/X86/mmx-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-shift.ll?rev=48627&r1=48626&r2=48627&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-shift.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-shift.ll Thu Mar 20 19:40:09 2008
@@ -3,12 +3,12 @@
define i64 @t1(<1 x i64> %mm1) nounwind {
entry:
- %tmp6 = tail call <1 x i64> @llvm.x86.mmx.pslli.q( <1 x i64> %mm1, i32 32 ) ; <<1 x i64>> [#uses=1]
+ %tmp6 = tail call <1 x i64> @llvm.x86.mmx.psll.q( <1 x i64> %mm1, <1 x i64> <i64 32> ) ; <<1 x i64>> [#uses=1]
%retval1112 = bitcast <1 x i64> %tmp6 to i64 ; <i64> [#uses=1]
ret i64 %retval1112
}
-declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone
+declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone
define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind {
entry:
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