[llvm-commits] [llvm] r48578 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll

[Evan Cheng]

Author: evancheng
Date: Wed Mar 19 21:18:41 2008
New Revision: 48578

URL: http://llvm.org/viewvc/llvm-project?rev=48578&view=rev
Log:
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))

Added:
    llvm/trunk/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=48578&r1=48577&r2=48578&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 19 21:18:41 2008
@@ -2400,7 +2400,9 @@
 
       // If the shift wouldn't be a noop, the truncated type is an actual type,
       // and the truncate is free, then proceed with the transform.
-      if (ShiftAmt != 0 && TLI.isTruncateFree(VT, TruncVT)) {
+      if (ShiftAmt != 0 &&
+          TLI.isTypeLegal(TruncVT) &&
+          TLI.isTruncateFree(VT, TruncVT)) {
         SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
         SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
         SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=48578&r1=48577&r2=48578&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Mar 19 21:18:41 2008
@@ -5662,7 +5662,7 @@
     return false;
   unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
   unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
-  if (NumBits1 <= NumBits2 || NumBits2 < 8)
+  if (NumBits1 <= NumBits2)
     return false;
   return Subtarget->is64Bit() || NumBits1 < 64;
 }
@@ -5673,7 +5673,7 @@
     return false;
   unsigned NumBits1 = MVT::getSizeInBits(VT1);
   unsigned NumBits2 = MVT::getSizeInBits(VT2);
-  if (NumBits1 <= NumBits2 || NumBits2 < 8)
+  if (NumBits1 <= NumBits2)
     return false;
   return Subtarget->is64Bit() || NumBits1 < 64;
 }

Added: llvm/trunk/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll?rev=48578&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll Wed Mar 19 21:18:41 2008
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86
+
+define i32 @t() nounwind  {
+entry:
+	%tmp54 = add i32 0, 1		; <i32> [#uses=1]
+	br i1 false, label %bb71, label %bb77
+bb71:		; preds = %entry
+	%tmp74 = shl i32 %tmp54, 1		; <i32> [#uses=1]
+	%tmp76 = ashr i32 %tmp74, 3		; <i32> [#uses=1]
+	br label %bb77
+bb77:		; preds = %bb71, %entry
+	%payLoadSize.0 = phi i32 [ %tmp76, %bb71 ], [ 0, %entry ]		; <i32> [#uses=0]
+	unreachable
+}