[llvm-commits] [llvm] r48381 - in /llvm/trunk: include/llvm/Target/TargetInstrDesc.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/Target/Target.td utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp

[Evan Cheng]

Author: evancheng
Date: Fri Mar 14 19:19:36 2008
New Revision: 48381

URL: http://llvm.org/viewvc/llvm-project?rev=48381&view=rev
Log:
Remove isImplicitDef TargetInstrDesc flag.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrDesc.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/Target/Target.td
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.h
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Fri Mar 14 19:19:36 2008
@@ -81,7 +81,6 @@
     HasOptionalDef,
     Return,
     Call,
-    ImplicitDef,
     Barrier,
     Terminator,
     Branch,
@@ -219,13 +218,6 @@
     return Flags & (1 << TID::Call);
   }
   
-  /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
-  /// which defines a register to an unspecified value.  These basically
-  /// correspond to x = undef.
-  bool isImplicitDef() const {
-    return Flags & (1 << TID::ImplicitDef);
-  }
-  
   /// isBarrier - Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Mar 14 19:19:36 2008
@@ -641,8 +641,7 @@
     return false;
 
   isLoad = false;
-  const TargetInstrDesc &TID = MI->getDesc();
-  if (TID.isImplicitDef())
+  if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
     return true;
 
   int FrameIdx = 0;
@@ -655,6 +654,7 @@
     return true;
 
   if (tii_->isTriviallyReMaterializable(MI)) {
+    const TargetInstrDesc &TID = MI->getDesc();
     isLoad = TID.isSimpleLoad();
 
     unsigned ImpUse = getReMatImplicitUse(li, MI);
@@ -741,9 +741,8 @@
                                          unsigned InstrIdx,
                                          SmallVector<unsigned, 2> &Ops,
                                          bool isSS, int Slot, unsigned Reg) {
-  const TargetInstrDesc &TID = MI->getDesc();
   // If it is an implicit def instruction, just delete it.
-  if (TID.isImplicitDef()) {
+  if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
     RemoveMachineInstrFromMaps(MI);
     vrm.RemoveMachineInstrFromMaps(MI);
     MI->eraseFromParent();

Modified: llvm/trunk/lib/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Target.td (original)
+++ llvm/trunk/lib/Target/Target.td Fri Mar 14 19:19:36 2008
@@ -193,7 +193,6 @@
   bit isSimpleLoad = 0;     // Is this just a load instruction?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?
-  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Mar 14 19:19:36 2008
@@ -86,7 +86,6 @@
   isSimpleLoad = R->getValueAsBit("isSimpleLoad");
   mayLoad      = R->getValueAsBit("mayLoad");
   mayStore     = R->getValueAsBit("mayStore");
-  isImplicitDef= R->getValueAsBit("isImplicitDef");
   bool isTwoAddress = R->getValueAsBit("isTwoAddress");
   isPredicable = R->getValueAsBit("isPredicable");
   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Fri Mar 14 19:19:36 2008
@@ -91,7 +91,6 @@
     bool isCall;
     bool isSimpleLoad;
     bool mayLoad, mayStore;
-    bool isImplicitDef;
     bool isPredicable;
     bool isConvertibleToThreeAddress;
     bool isCommutable;

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=48381&r1=48380&r2=48381&view=diff

==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Fri Mar 14 19:19:36 2008
@@ -346,7 +346,6 @@
   if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
   if (mayLoad)           OS << "|(1<<TID::MayLoad)";
   if (mayStore)          OS << "|(1<<TID::MayStore)";
-  if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
   if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
   if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
   if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";