[llvm-commits] Fwd: [llvm] r48223 - in /llvm/trunk/lib: CodeGen/LowerSubregs.cpp CodeGen/SelectionDAG/ScheduleDAG.cpp Target/Target.td Target/X86/X86ISelDAGToDAG.cpp Target/X86/X86InstrInfo.h Target/X86/X86InstrInfo.td Target/X86/X86RegisterInfo.h Target/X86/X86RegisterInfo.td

[Chris Lattner]

>> allocator" to delete these things when it "converts out of ssa".   
>> I've
>> seen many cases when live ranges from IMPLICIT_DEF end up eating a
>> register (causing something to get spilled or an extra copy) and
>> otherwise wreak havok.  Having "ssa elimination" just delete live
>> ranges/value numbers that are defined by an IMPLICIT_DEF (and also
>> deleting the IMPLICIT_DEF itself) seems like an easy and natural way
>> to handle this.
>
> I agree with this in general although I am not certain of the
> implementation complexity.
>
> vr1024 = undef
> ...
> ...
> vr1025 = op vr1024, ?
>
> How would we model vr1024? A single cycle live interval? Or better
> yet, don't allocate it and let rewriter assign it an arbitrary
> register? That seems like goodness to me.

A zero cycle live interval.  It should have no live ranges, because it  
can't conflict with anything.

>> This is orthogonal from the subreg stuff of course.
>
> Yep.

However, getting this right can potentially simplify the subreg stuff  
and eliminate some other random hacky code for handling implicit_def's  
in the compiler.

-Chris