[llvm-commits] [llvm] r48130 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/LowerSubregs.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/Target/Target.td lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.h lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86RegisterInfo.h lib/Target/X86/X86RegisterInfo.td

[Dan Gohman]

On Mar 11, 2008, at 12:19 AM, Christopher Lamb wrote:
>
>> I'm not sure I completely understand this. Are you saying  
>> insert_subreg, extract_subreg isel patterns checks for memoperands?  
>> Why would there be any?
>
> The reason that there would be any memoperands is that the  
> DAGIselEmiter generates isel code which always attaches memoperands  
> for a pattern containing loads and stores to the root node of the  
> generated instruction pattern.
>
> So a theoretical pattern:
>
> Pat<(zextloadi8 B), (SHR (SHL (LOAD B), 24), 24)>;
>
> will have the memoperands attached to the generated SHR node. In  
> addition it appears that a chain operand may be added to the SHR,  
> and SHL nodes as well.

I don't think there's a reason MemOperand nodes have to be on
the root node. And actually, I think it would be better to
attach them to the load/store node directly.

Dan