[llvm-commits] [llvm] r48208 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Author: lattner
Date: Mon Mar 10 22:14:42 2008
New Revision: 48208

URL: http://llvm.org/viewvc/llvm-project?rev=48208&view=rev
Log:
variadic instructions don't have operand info for variadic arguments.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=48208&r1=48207&r2=48208&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Mar 10 22:14:42 2008
@@ -538,6 +538,7 @@
       // the regclass is ok.
       const TargetRegisterClass *RC =
                           getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
+      assert((RC || II->isVariadic()) && "Expected reg class info!");
       const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
       if (RC && VRC != RC) {
         cerr << "Register class of operand and regclass of use don't agree!\n";
@@ -604,7 +605,7 @@
     // to be able to handle it.  This handles things like copies from ST(0) to
     // an FP vreg on x86.
     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
-    if (II) {
+    if (II && !II->isVariadic()) {
       assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
              "Don't have operand info for this instruction!");
     }