[llvm-commits] [llvm] r48119 - /llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp

[Chris Lattner]

Author: lattner
Date: Sun Mar  9 15:31:11 2008
New Revision: 48119

URL: http://llvm.org/viewvc/llvm-project?rev=48119&view=rev
Log:
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=48119&r1=48118&r2=48119&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Sun Mar  9 15:31:11 2008
@@ -186,10 +186,15 @@
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const
 {
-  if (DestRC != SrcRC) {
-    cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
-    abort();
-  }
+  // We support cross register class moves for our aliases, such as R3 in any
+  // reg class to any other reg class containing R3.  This is required because
+  // we instruction select bitconvert i64 -> f64 as a noop for example, so our
+  // types have no specific meaning.
+  
+  //if (DestRC != SrcRC) {
+  //  cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+  //  abort();
+  //}
 
   if (DestRC == SPU::R8CRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);