[llvm-commits] [llvm] r48098 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td

[Chris Lattner]

Author: lattner
Date: Sun Mar  9 01:49:01 2008
New Revision: 48098

URL: http://llvm.org/viewvc/llvm-project?rev=48098&view=rev
Log:
claim ST(x) registers are 80 bits, which is true.  This doesn't affect 
codegen yet because these can't be spilled (they don't exist until after RA).

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=48098&r1=48097&r2=48098&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Sun Mar  9 01:49:01 2008
@@ -488,7 +488,7 @@
 // Floating point stack registers (these are not allocatable by the
 // register allocator - the floating point stackifier is responsible
 // for transforming FPn allocations to STn registers)
-def RST : RegisterClass<"X86", [f64], 32,
+def RST : RegisterClass<"X86", [f80], 32,
                         [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
     let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;