[llvm-commits] [llvm] r47625 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ utils/TableGen/
Evan Cheng
evan.cheng at apple.com
Tue Feb 26 13:34:27 PST 2008
Is getPrintableName() going to be eliminated?
Evan
On Feb 26, 2008, at 1:11 PM, Bill Wendling wrote:
> Author: void
> Date: Tue Feb 26 15:11:01 2008
> New Revision: 47625
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47625&view=rev
> Log:
> Change "Name" to "AsmName" in the target register info. Gee, a
> refactoring tool
> would have been a Godsend here!
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/lib/CodeGen/LiveInterval.cpp
> llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
> llvm/trunk/lib/CodeGen/MachineFunction.cpp
> llvm/trunk/lib/CodeGen/MachineLICM.cpp
> llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
> llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> llvm/trunk/lib/CodeGen/VirtRegMap.cpp
> llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp
> llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
> llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
> llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp
> llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
> llvm/trunk/lib/Target/Target.td
> llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
> llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
> llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h
> llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Feb 26
> 15:11:01 2008
> @@ -48,7 +48,7 @@
> /// register, e.g. RAX, EAX, are super-registers of AX.
> ///
> struct TargetRegisterDesc {
> - const char *Name; // Assembly language name for the
> register
> + const char *AsmName; // Assembly language name for the
> register
> const char *PrintableName;// Printable name for the reg (for
> debugging)
> const unsigned *AliasSet; // Register Alias Set, described above
> const unsigned *SubRegs; // Sub-register set, described above
> @@ -376,10 +376,10 @@
> return get(RegNo).SuperRegs;
> }
>
> - /// getName - Return the symbolic target specific name for the
> specified
> - /// physical register.
> - const char *getName(unsigned RegNo) const {
> - return get(RegNo).Name;
> + /// getAsmName - Return the symbolic target specific name for the
> + /// specified physical register.
> + const char *getAsmName(unsigned RegNo) const {
> + return get(RegNo).AsmName;
> }
>
> /// getPrintableName - Return the human-readable symbolic target
> specific name
>
> Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Feb 26 15:11:01 2008
> @@ -665,7 +665,7 @@
> void LiveInterval::print(std::ostream &OS,
> const TargetRegisterInfo *TRI) const {
> if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
> - OS << TRI->getName(reg);
> + OS << TRI->getPrintableName(reg);
> else
> OS << "%reg" << reg;
>
>
> Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Feb 26
> 15:11:01 2008
> @@ -189,7 +189,7 @@
>
> void LiveIntervals::printRegName(unsigned reg) const {
> if (TargetRegisterInfo::isPhysicalRegister(reg))
> - cerr << tri_->getName(reg);
> + cerr << tri_->getPrintableName(reg);
> else
> cerr << "%reg" << reg;
> }
>
> Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Feb 26 15:11:01
> 2008
> @@ -146,7 +146,7 @@
> const TargetRegisterInfo *TRI = 0) {
> if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
> if (TRI)
> - os << " %" << TRI->get(RegNo).Name;
> + os << " %" << TRI->get(RegNo).PrintableName;
> else
> os << " %mreg(" << RegNo << ")";
> } else
>
> Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Feb 26 15:11:01
> 2008
> @@ -214,7 +214,7 @@
> for (MachineRegisterInfo::livein_iterator
> I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I !
> = E; ++I) {
> if (TRI)
> - OS << " " << TRI->getName(I->first);
> + OS << " " << TRI->getPrintableName(I->first);
> else
> OS << " Reg #" << I->first;
>
> @@ -228,7 +228,7 @@
> for (MachineRegisterInfo::liveout_iterator
> I = RegInfo->liveout_begin(), E = RegInfo->liveout_end();
> I != E; ++I)
> if (TRI)
> - OS << " " << TRI->getName(*I);
> + OS << " " << TRI->getPrintableName(*I);
> else
> OS << " Reg #" << *I;
> OS << "\n";
>
> Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Feb 26 15:11:01 2008
> @@ -251,7 +251,7 @@
> const TargetRegisterInfo *TRI = TM->getRegisterInfo();
> for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
> *ImpUses; ++ImpUses)
> - DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
> + DOUT << " -> " << TRI->getPrintableName(*ImpUses) <<
> "\n";
> }
>
> if (I.getDesc().getImplicitDefs()) {
> @@ -260,7 +260,7 @@
> const TargetRegisterInfo *TRI = TM->getRegisterInfo();
> for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
> *ImpDefs; ++ImpDefs)
> - DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
> + DOUT << " -> " << TRI->getPrintableName(*ImpDefs) <<
> "\n";
> }
>
> //if (TII->hasUnmodelledSideEffects(&I))
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Tue Feb 26 15:11:01
> 2008
> @@ -311,7 +311,7 @@
> assert(VirtReg && "Spilling a physical register is illegal!"
> " Must not have appropriate kill for the register or use
> exists beyond"
> " the intended one.");
> - DOUT << " Spilling register " << RegInfo->getName(PhysReg)
> + DOUT << " Spilling register " << RegInfo-
> >getPrintableName(PhysReg)
> << " containing %reg" << VirtReg;
>
> const TargetInstrInfo* TII = MBB.getParent()-
> >getTarget().getInstrInfo();
> @@ -535,7 +535,7 @@
> markVirtRegModified(VirtReg, false);
>
> DOUT << " Reloading %reg" << VirtReg << " into "
> - << RegInfo->getName(PhysReg) << "\n";
> + << RegInfo->getPrintableName(PhysReg) << "\n";
>
> // Add move instruction(s)
> TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
> @@ -646,7 +646,7 @@
> DOUT << " Regs have values: ";
> for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
> if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
> - DOUT << "[" << RegInfo->getName(i)
> + DOUT << "[" << RegInfo->getPrintableName(i)
> << ",%reg" << PhysRegsUsed[i] << "] ";
> DOUT << "\n");
>
> @@ -700,14 +700,14 @@
> }
>
> if (PhysReg) {
> - DOUT << " Last use of " << RegInfo->getName(PhysReg)
> + DOUT << " Last use of " << RegInfo-
> >getPrintableName(PhysReg)
> << "[%reg" << VirtReg <<"], removing it from live set\n";
> removePhysReg(PhysReg);
> for (const unsigned *AliasSet = RegInfo-
> >getSubRegisters(PhysReg);
> *AliasSet; ++AliasSet) {
> if (PhysRegsUsed[*AliasSet] != -2) {
> DOUT << " Last use of "
> - << RegInfo->getName(*AliasSet)
> + << RegInfo->getPrintableName(*AliasSet)
> << "[%reg" << VirtReg <<"], removing it from live
> set\n";
> removePhysReg(*AliasSet);
> }
> @@ -806,14 +806,14 @@
> }
>
> if (PhysReg) {
> - DOUT << " Register " << RegInfo->getName(PhysReg)
> + DOUT << " Register " << RegInfo->getPrintableName(PhysReg)
> << " [%reg" << VirtReg
> << "] is never used, removing it frame live list\n";
> removePhysReg(PhysReg);
> for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
> *AliasSet; ++AliasSet) {
> if (PhysRegsUsed[*AliasSet] != -2) {
> - DOUT << " Register " << RegInfo->getName(*AliasSet)
> + DOUT << " Register " << RegInfo-
> >getPrintableName(*AliasSet)
> << " [%reg" << *AliasSet
> << "] is never used, removing it frame live list\n";
> removePhysReg(*AliasSet);
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Tue Feb 26
> 15:11:01 2008
> @@ -164,7 +164,7 @@
> if (TargetRegisterInfo::isVirtualRegister(reg)) {
> reg = vrm_->getPhys(reg);
> }
> - DOUT << tri_->getName(reg) << '\n';
> + DOUT << tri_->getPrintableName(reg) << '\n';
> }
> }
> };
> @@ -239,7 +239,8 @@
>
> // Try to coalesce.
> if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
> - DOUT << "Coalescing: " << cur << " -> " << tri_-
> >getName(SrcReg) << '\n';
> + DOUT << "Coalescing: " << cur << " -> " << tri_-
> >getPrintableName(SrcReg)
> + << '\n';
> vrm_->clearVirt(cur.reg);
> vrm_->assignVirt2Phys(cur.reg, SrcReg);
> ++NumCoalesce;
> @@ -627,7 +628,7 @@
> // the free physical register and add this interval to the active
> // list.
> if (physReg) {
> - DOUT << tri_->getName(physReg) << '\n';
> + DOUT << tri_->getPrintableName(physReg) << '\n';
> vrm_->assignVirt2Phys(cur->reg, physReg);
> prt_->addRegUse(physReg);
> active_.push_back(std::make_pair(cur, cur->begin()));
> @@ -689,7 +690,7 @@
> }
>
> DOUT << "\t\tregister with min weight: "
> - << tri_->getName(minReg) << " (" << minWeight << ")\n";
> + << tri_->getPrintableName(minReg) << " (" << minWeight << ")
> \n";
>
> // if the current has the minimum weight, we need to spill it and
> // add any added intervals back to unhandled, and restart
> @@ -868,11 +869,11 @@
> if (cur->preference) {
> if (prt_->isRegAvail(cur->preference)) {
> DOUT << "\t\tassigned the preferred register: "
> - << tri_->getName(cur->preference) << "\n";
> + << tri_->getPrintableName(cur->preference) << "\n";
> return cur->preference;
> } else
> DOUT << "\t\tunable to assign the preferred register: "
> - << tri_->getName(cur->preference) << "\n";
> + << tri_->getPrintableName(cur->preference) << "\n";
> }
>
> // Scan for the first available register.
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Tue Feb 26 15:11:01 2008
> @@ -286,7 +286,7 @@
> assert(VirtReg && "Spilling a physical register is illegal!"
> " Must not have appropriate kill for the register or use
> exists beyond"
> " the intended one.");
> - DOUT << " Spilling register " << TRI->getName(PhysReg)
> + DOUT << " Spilling register " << TRI->getPrintableName(PhysReg)
> << " containing %reg" << VirtReg;
>
> const TargetInstrInfo* TII = MBB.getParent()-
> >getTarget().getInstrInfo();
> @@ -502,7 +502,7 @@
> markVirtRegModified(VirtReg, false); // Note that this reg was
> just reloaded
>
> DOUT << " Reloading %reg" << VirtReg << " into "
> - << TRI->getName(PhysReg) << "\n";
> + << TRI->getPrintableName(PhysReg) << "\n";
>
> // Add move instruction(s)
> const TargetInstrInfo* TII = MBB.getParent()-
> >getTarget().getInstrInfo();
> @@ -575,7 +575,7 @@
> DOUT << " Regs have values: ";
> for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
> if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
> - DOUT << "[" << TRI->getName(i)
> + DOUT << "[" << TRI->getPrintableName(i)
> << ",%reg" << PhysRegsUsed[i] << "] ";
> DOUT << "\n");
>
> @@ -637,14 +637,14 @@
> }
>
> if (PhysReg) {
> - DOUT << " Last use of " << TRI->getName(PhysReg)
> + DOUT << " Last use of " << TRI->getPrintableName(PhysReg)
> << "[%reg" << VirtReg <<"], removing it from live set\n";
> removePhysReg(PhysReg);
> for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
> *AliasSet; ++AliasSet) {
> if (PhysRegsUsed[*AliasSet] != -2) {
> DOUT << " Last use of "
> - << TRI->getName(*AliasSet)
> + << TRI->getPrintableName(*AliasSet)
> << "[%reg" << VirtReg <<"], removing it from live
> set\n";
> removePhysReg(*AliasSet);
> }
> @@ -728,7 +728,7 @@
> MF->getRegInfo().setPhysRegUsed(DestPhysReg);
> markVirtRegModified(DestVirtReg);
> getVirtRegLastUse(DestVirtReg) =
> std::make_pair((MachineInstr*)0, 0);
> - DOUT << " Assigning " << TRI->getName(DestPhysReg)
> + DOUT << " Assigning " << TRI->getPrintableName(DestPhysReg)
> << " to %reg" << DestVirtReg << "\n";
> MI->getOperand(i).setReg(DestPhysReg); // Assign the output
> register
> }
> @@ -751,14 +751,14 @@
> }
>
> if (PhysReg) {
> - DOUT << " Register " << TRI->getName(PhysReg)
> + DOUT << " Register " << TRI->getPrintableName(PhysReg)
> << " [%reg" << VirtReg
> << "] is never used, removing it frame live list\n";
> removePhysReg(PhysReg);
> for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
> *AliasSet; ++AliasSet) {
> if (PhysRegsUsed[*AliasSet] != -2) {
> - DOUT << " Register " << TRI->getName(*AliasSet)
> + DOUT << " Register " << TRI-
> >getPrintableName(*AliasSet)
> << " [%reg" << *AliasSet
> << "] is never used, removing it frame live list\n";
> removePhysReg(*AliasSet);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 26
> 15:11:01 2008
> @@ -4181,7 +4181,8 @@
> } else if (const RegisterSDNode *R =
> dyn_cast<RegisterSDNode>(this)) {
> if (G && R->getReg() &&
> TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
> - cerr << " " <<G->getTarget().getRegisterInfo()->getName(R-
> >getReg());
> + cerr << " "
> + << G->getTarget().getRegisterInfo()->getPrintableName(R-
> >getReg());
> } else {
> cerr << " #" << R->getReg();
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue
> Feb 26 15:11:01 2008
> @@ -133,7 +133,8 @@
> } else if (const RegisterSDNode *R =
> dyn_cast<RegisterSDNode>(Node)) {
> if (G && R->getReg() != 0 &&
> TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
> - Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R-
> >getReg());
> + Op = Op + " " +
> + G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
> } else {
> Op += " #" + utostr(R->getReg());
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Feb
> 26 15:11:01 2008
> @@ -1648,7 +1648,7 @@
>
> for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
> I != E; ++I) {
> - if (StringsEqualNoCase(RegName, RI->get(*I).Name))
> + if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
> return std::make_pair(*I, RC);
> }
> }
>
> Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Feb 26
> 15:11:01 2008
> @@ -1537,7 +1537,7 @@
>
> void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
> if (TargetRegisterInfo::isPhysicalRegister(reg))
> - cerr << tri_->getName(reg);
> + cerr << tri_->getPrintableName(reg);
> else
> cerr << "%reg" << reg;
> }
>
> Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
> +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Feb 26 15:11:01 2008
> @@ -141,8 +141,8 @@
> for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
> e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
> if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
> - OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
> << "]\n";
> -
> + OS << "[reg" << i << " -> " << TRI-
> >getPrintableName(Virt2PhysMap[i])
> + << "]\n";
> }
>
> for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
> @@ -351,7 +351,7 @@
> DOUT << "Remembering RM#" << SlotOrReMat-
> VirtRegMap::MAX_STACK_SLOT-1;
> else
> DOUT << "Remembering SS#" << SlotOrReMat;
> - DOUT << " in physreg " << TRI->getName(Reg) << "\n";
> + DOUT << " in physreg " << TRI->getPrintableName(Reg) << "\n";
> }
>
> /// canClobberPhysReg - Return true if the spiller is allowed to
> change the
> @@ -392,7 +392,7 @@
> assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) ==
> PhysReg &&
> "Bidirectional map mismatch!");
> SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
> - DOUT << "PhysReg " << TRI->getName(PhysReg)
> + DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
> << " copied, it is available for use but can no longer be
> modified\n";
> }
> }
> @@ -417,7 +417,7 @@
> assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) ==
> PhysReg &&
> "Bidirectional map mismatch!");
> SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
> - DOUT << "PhysReg " << TRI->getName(PhysReg)
> + DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
> << " clobbered, invalidating ";
> if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
> DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 <<
> "\n";
> @@ -1135,9 +1135,9 @@
> else
> DOUT << "Reusing SS#" << ReuseSlot;
> DOUT << " from physreg "
> - << TRI->getName(PhysReg) << " for vreg"
> + << TRI->getPrintableName(PhysReg) << " for vreg"
> << VirtReg <<" instead of reloading into physreg "
> - << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
> + << TRI->getPrintableName(VRM.getPhys(VirtReg)) <<
> "\n";
> unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) :
> PhysReg;
> MI.getOperand(i).setReg(RReg);
>
> @@ -1208,8 +1208,8 @@
> DOUT << "Reusing RM#" << ReuseSlot-
> VirtRegMap::MAX_STACK_SLOT-1;
> else
> DOUT << "Reusing SS#" << ReuseSlot;
> - DOUT << " from physreg " << TRI->getName(PhysReg) << "
> for vreg"
> - << VirtReg
> + DOUT << " from physreg " << TRI->getPrintableName(PhysReg)
> + << " for vreg" << VirtReg
> << " instead of reloading into same physreg.\n";
> unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) :
> PhysReg;
> MI.getOperand(i).setReg(RReg);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Feb 26 15:11:01
> 2008
> @@ -273,7 +273,7 @@
> switch (MO.getType()) {
> case MachineOperand::MO_Register:
> if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> else
> assert(0 && "not implemented");
> break;
> @@ -393,7 +393,7 @@
> const MachineOperand &MO3 = MI->getOperand(Op+2);
>
> assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
> - O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
>
> // Print the shift opc.
> O << ", "
> @@ -402,7 +402,7 @@
>
> if (MO2.getReg()) {
> assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
> - O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
> assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
> } else {
> O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
> @@ -419,7 +419,7 @@
> return;
> }
>
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
>
> if (!MO2.getReg()) {
> if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
> @@ -432,7 +432,7 @@
>
> O << ", "
> << (char)ARM_AM::getAM2Op(MO3.getImm())
> - << TM.getRegisterInfo()->get(MO2.getReg()).Name;
> + << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
>
> if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
> O << ", "
> @@ -455,7 +455,7 @@
> }
>
> O << (char)ARM_AM::getAM2Op(MO2.getImm())
> - << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
>
> if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
> O << ", "
> @@ -469,12 +469,12 @@
> const MachineOperand &MO3 = MI->getOperand(Op+2);
>
> assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
>
> if (MO2.getReg()) {
> O << ", "
> << (char)ARM_AM::getAM3Op(MO3.getImm())
> - << TM.getRegisterInfo()->get(MO2.getReg()).Name
> + << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
> << "]";
> return;
> }
> @@ -492,7 +492,7 @@
>
> if (MO1.getReg()) {
> O << (char)ARM_AM::getAM3Op(MO2.getImm())
> - << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
> return;
> }
>
> @@ -545,13 +545,13 @@
> return;
> } else if (Modifier && strcmp(Modifier, "base") == 0) {
> // Used for FSTM{D|S} and LSTM{D|S} operations.
> - O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
> if (ARM_AM::getAM5WBFlag(MO2.getImm()))
> O << "!";
> return;
> }
>
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
>
> if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
> O << ", #"
> @@ -570,15 +570,15 @@
>
> const MachineOperand &MO1 = MI->getOperand(Op);
> assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
> - O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name <<
> "]";
> + O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName
> << "]";
> }
>
> void
> ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI,
> int Op) {
> const MachineOperand &MO1 = MI->getOperand(Op);
> const MachineOperand &MO2 = MI->getOperand(Op+1);
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> - O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).Name << "]";
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
> + O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName <<
> "]";
> }
>
> void
> @@ -593,9 +593,9 @@
> return;
> }
>
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
> if (MO3.getReg())
> - O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).Name;
> + O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
> else if (unsigned ImmOffs = MO2.getImm()) {
> O << ", #" << ImmOffs;
> if (Scale > 1)
> @@ -620,7 +620,7 @@
> void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr
> *MI,int Op) {
> const MachineOperand &MO1 = MI->getOperand(Op);
> const MachineOperand &MO2 = MI->getOperand(Op+1);
> - O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
> + O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
> if (unsigned ImmOffs = MO2.getImm())
> O << ", #" << ImmOffs << " * 4";
> O << "]";
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -77,7 +77,7 @@
> if (MO.getType() == MachineOperand::MO_Register) {
> assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
> "Not physreg??");
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> } else if (MO.isImmediate()) {
> O << MO.getImm();
> assert(MO.getImm() < (1 << 30));
> @@ -92,7 +92,7 @@
>
> switch (MO.getType()) {
> case MachineOperand::MO_Register:
> - O << RI.get(MO.getReg()).Name;
> + O << RI.get(MO.getReg()).AsmName;
> return;
>
> case MachineOperand::MO_Immediate:
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Feb 26
> 15:11:01 2008
> @@ -334,6 +334,6 @@
>
> std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
> {
> - std::string s(RegisterDescriptors[reg].Name);
> + std::string s(RegisterDescriptors[reg].PrintableName);
> return s;
> }
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -75,14 +75,14 @@
> unsigned RegNo = MO.getReg();
> assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
> "Not physreg??");
> - O << TM.getRegisterInfo()->get(RegNo).Name;
> + O << TM.getRegisterInfo()->get(RegNo).AsmName;
> }
>
> void printOperand(const MachineInstr *MI, unsigned OpNo) {
> const MachineOperand &MO = MI->getOperand(OpNo);
> if (MO.isRegister()) {
>
> assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not
> physreg??");
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> } else if (MO.isImmediate()) {
> O << MO.getImm();
> } else {
> @@ -149,7 +149,7 @@
> // the value contained in the register. For this reason, the
> darwin
> // assembler requires that we print r0 as 0 (no r) when used
> as the base.
> const MachineOperand &MO = MI->getOperand(OpNo);
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> O << ", ";
> printOperand(MI, OpNo+1);
> }
>
> Modified: llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -56,7 +56,7 @@
> assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
> "Not physref??");
> //XXX Bug Workaround: See note in Printer::doInitialization
> about %.
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> } else {
> printOp(MO);
> }
> @@ -168,7 +168,7 @@
> const TargetRegisterInfo &RI = *TM.getRegisterInfo();
> switch (MO.getType()) {
> case MachineOperand::MO_Register:
> - O << RI.get(MO.getReg()).Name;
> + O << RI.get(MO.getReg()).AsmName;
> return;
>
> case MachineOperand::MO_Immediate:
>
> Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -169,9 +169,9 @@
> unsigned stackSize = MF.getFrameInfo()->getStackSize();
>
>
> - O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).Name)
> + O << "\t.frame\t" << "$" <<
> LowercaseString(RI.get(stackReg).AsmName)
> << "," << stackSize << ","
> - << "$" << LowercaseString(RI.get(returnReg).Name)
> + << "$" <<
> LowercaseString(RI.get(returnReg).AsmName)
> << "\n";
> }
>
> @@ -365,7 +365,7 @@
> {
> case MachineOperand::MO_Register:
> if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
> - O << "$" << LowercaseString (RI.get(MO.getReg()).Name);
> + O << "$" << LowercaseString (RI.get(MO.getReg()).AsmName);
> else
> O << "$" << MO.getReg();
> break;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -113,7 +113,7 @@
> return;
> }
>
> - const char *RegName = TM.getRegisterInfo()->get(RegNo).Name;
> + const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
> // Linux assembler (Others?) does not take register mnemonics.
> // FIXME - What about special registers used in mfspr/mtspr?
> if (!Subtarget.isDarwin()) RegName =
> stripRegisterPrefix(RegName);
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Tue Feb 26
> 15:11:01 2008
> @@ -22,7 +22,7 @@
> }
>
> // GP8 - One of the 32 64-bit general-purpose registers
> -class GP8<GPR SubReg, string n> : PPCReg<SubReg.Name> {
> +class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
> field bits<5> Num = SubReg.Num;
> let SubRegs = [SubReg];
> let PrintableName = n;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -146,7 +146,7 @@
> switch (MO.getType()) {
> case MachineOperand::MO_Register:
> if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
> - O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
> + O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
> else
> O << "%reg" << MO.getReg();
> break;
>
> Modified: llvm/trunk/lib/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/Target.td (original)
> +++ llvm/trunk/lib/Target/Target.td Tue Feb 26 15:11:01 2008
> @@ -25,7 +25,7 @@
> // in the target machine. String n will become the "name" of the
> register.
> class Register<string n> {
> string Namespace = "";
> - string Name = n;
> + string AsmName = n;
> string PrintableName = n;
>
> // SpillSize - If this value is set to a non-zero value, it is the
> size in
>
> Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -229,7 +229,7 @@
> ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 :
> MVT::i8));
> Reg = getX86SubSuperRegister(Reg, VT);
> }
> - for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
> + for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
> O << (char)tolower(*Name);
> return;
> }
> @@ -575,7 +575,7 @@
> }
>
> O << '%';
> - for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
> + for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
> O << (char)tolower(*Name);
> return false;
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -125,7 +125,7 @@
> ((strcmp(Modifier,"subreg16") == 0) ?
> MVT::i16 :MVT::i8));
> Reg = getX86SubSuperRegister(Reg, VT);
> }
> - O << RI.get(Reg).Name;
> + O << RI.get(Reg).AsmName;
> } else
> O << "reg" << MO.getReg();
> return;
> @@ -271,7 +271,7 @@
> break;
> }
>
> - O << '%' << RI.get(Reg).Name;
> + O << '%' << RI.get(Reg).AsmName;
> return false;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h Tue Feb 26
> 15:11:01 2008
> @@ -43,7 +43,7 @@
> if (MO.isRegister()) {
> assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
> "Not physreg??");
> - O << TM.getRegisterInfo()->get(MO.getReg()).Name;
> + O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
> } else {
> printOp(MO, Modifier);
> }
>
> Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=47625&r1=47624&r2=47625&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Feb 26
> 15:11:01 2008
> @@ -520,8 +520,8 @@
> for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
> const CodeGenRegister &Reg = Registers[i];
> OS << " { \"";
> - if (!Reg.TheDef->getValueAsString("Name").empty())
> - OS << Reg.TheDef->getValueAsString("Name");
> + if (!Reg.TheDef->getValueAsString("AsmName").empty())
> + OS << Reg.TheDef->getValueAsString("AsmName");
> else
> OS << Reg.getName();
> OS << "\",\t\"";
>
>
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