[llvm-commits] [llvm] r47534 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/MachineInstr.cpp lib/Target/PowerPC/PPCRegisterInfo.td lib/Target/Target.td utils/TableGen/RegisterInfoEmitter.cpp
Bill Wendling
isanbard at gmail.com
Sat Feb 23 16:56:14 PST 2008
Author: void
Date: Sat Feb 23 18:56:13 2008
New Revision: 47534
URL: http://llvm.org/viewvc/llvm-project?rev=47534&view=rev
Log:
Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
Modified:
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/lib/Target/Target.td
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=47534&r1=47533&r2=47534&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sat Feb 23 18:56:13 2008
@@ -49,6 +49,7 @@
///
struct TargetRegisterDesc {
const char *Name; // Assembly language name for the register
+ const char *PrintableName;// Printable name for the reg (for debugging)
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
const unsigned *ImmSubRegs; // Immediate sub-register set, described above
@@ -381,6 +382,12 @@
return get(RegNo).Name;
}
+ /// getPrintableName - Return the human-readable symbolic target specific name
+ /// for the specified physical register.
+ const char *getPrintableName(unsigned RegNo) const {
+ return get(RegNo).PrintableName;
+ }
+
/// getNumRegs - Return the number of registers this target has (useful for
/// sizing arrays holding per register information)
unsigned getNumRegs() const {
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47534&r1=47533&r2=47534&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sat Feb 23 18:56:13 2008
@@ -174,7 +174,7 @@
TM = &MF->getTarget();
if (TM)
- OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
+ OS << "%" << TM->getRegisterInfo()->get(getReg()).PrintableName;
else
OS << "%mreg" << getReg();
}
@@ -190,9 +190,9 @@
NeedComma = true;
}
if (isKill() || isDead()) {
- if (NeedComma) OS << ",";
- if (isKill()) OS << "kill";
- if (isDead()) OS << "dead";
+ if (NeedComma) OS << ",";
+ if (isKill()) OS << "kill";
+ if (isDead()) OS << "dead";
}
OS << ">";
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=47534&r1=47533&r2=47534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Sat Feb 23 18:56:13 2008
@@ -1,4 +1,4 @@
-//===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
+//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -22,9 +22,10 @@
}
// GP8 - One of the 32 64-bit general-purpose registers
-class GP8<GPR SubReg> : PPCReg<SubReg.Name> {
+class GP8<GPR SubReg, string n> : PPCReg<SubReg.Name> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
+ let PrintableName = n;
}
// SPR - One of the 32-bit special-purpose registers
@@ -88,38 +89,38 @@
def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
// 64-bit General-purpose registers
-def X0 : GP8< R0>, DwarfRegNum<[0]>;
-def X1 : GP8< R1>, DwarfRegNum<[1]>;
-def X2 : GP8< R2>, DwarfRegNum<[2]>;
-def X3 : GP8< R3>, DwarfRegNum<[3]>;
-def X4 : GP8< R4>, DwarfRegNum<[4]>;
-def X5 : GP8< R5>, DwarfRegNum<[5]>;
-def X6 : GP8< R6>, DwarfRegNum<[6]>;
-def X7 : GP8< R7>, DwarfRegNum<[7]>;
-def X8 : GP8< R8>, DwarfRegNum<[8]>;
-def X9 : GP8< R9>, DwarfRegNum<[9]>;
-def X10 : GP8<R10>, DwarfRegNum<[10]>;
-def X11 : GP8<R11>, DwarfRegNum<[11]>;
-def X12 : GP8<R12>, DwarfRegNum<[12]>;
-def X13 : GP8<R13>, DwarfRegNum<[13]>;
-def X14 : GP8<R14>, DwarfRegNum<[14]>;
-def X15 : GP8<R15>, DwarfRegNum<[15]>;
-def X16 : GP8<R16>, DwarfRegNum<[16]>;
-def X17 : GP8<R17>, DwarfRegNum<[17]>;
-def X18 : GP8<R18>, DwarfRegNum<[18]>;
-def X19 : GP8<R19>, DwarfRegNum<[19]>;
-def X20 : GP8<R20>, DwarfRegNum<[20]>;
-def X21 : GP8<R21>, DwarfRegNum<[21]>;
-def X22 : GP8<R22>, DwarfRegNum<[22]>;
-def X23 : GP8<R23>, DwarfRegNum<[23]>;
-def X24 : GP8<R24>, DwarfRegNum<[24]>;
-def X25 : GP8<R25>, DwarfRegNum<[25]>;
-def X26 : GP8<R26>, DwarfRegNum<[26]>;
-def X27 : GP8<R27>, DwarfRegNum<[27]>;
-def X28 : GP8<R28>, DwarfRegNum<[28]>;
-def X29 : GP8<R29>, DwarfRegNum<[29]>;
-def X30 : GP8<R30>, DwarfRegNum<[30]>;
-def X31 : GP8<R31>, DwarfRegNum<[31]>;
+def X0 : GP8< R0, "x0">, DwarfRegNum<[0]>;
+def X1 : GP8< R1, "x1">, DwarfRegNum<[1]>;
+def X2 : GP8< R2, "x2">, DwarfRegNum<[2]>;
+def X3 : GP8< R3, "x3">, DwarfRegNum<[3]>;
+def X4 : GP8< R4, "x4">, DwarfRegNum<[4]>;
+def X5 : GP8< R5, "x5">, DwarfRegNum<[5]>;
+def X6 : GP8< R6, "x6">, DwarfRegNum<[6]>;
+def X7 : GP8< R7, "x7">, DwarfRegNum<[7]>;
+def X8 : GP8< R8, "x8">, DwarfRegNum<[8]>;
+def X9 : GP8< R9, "x9">, DwarfRegNum<[9]>;
+def X10 : GP8<R10, "x10">, DwarfRegNum<[10]>;
+def X11 : GP8<R11, "x11">, DwarfRegNum<[11]>;
+def X12 : GP8<R12, "x12">, DwarfRegNum<[12]>;
+def X13 : GP8<R13, "x13">, DwarfRegNum<[13]>;
+def X14 : GP8<R14, "x14">, DwarfRegNum<[14]>;
+def X15 : GP8<R15, "x15">, DwarfRegNum<[15]>;
+def X16 : GP8<R16, "x16">, DwarfRegNum<[16]>;
+def X17 : GP8<R17, "x17">, DwarfRegNum<[17]>;
+def X18 : GP8<R18, "x18">, DwarfRegNum<[18]>;
+def X19 : GP8<R19, "x19">, DwarfRegNum<[19]>;
+def X20 : GP8<R20, "x20">, DwarfRegNum<[20]>;
+def X21 : GP8<R21, "x21">, DwarfRegNum<[21]>;
+def X22 : GP8<R22, "x22">, DwarfRegNum<[22]>;
+def X23 : GP8<R23, "x23">, DwarfRegNum<[23]>;
+def X24 : GP8<R24, "x24">, DwarfRegNum<[24]>;
+def X25 : GP8<R25, "x25">, DwarfRegNum<[25]>;
+def X26 : GP8<R26, "x26">, DwarfRegNum<[26]>;
+def X27 : GP8<R27, "x27">, DwarfRegNum<[27]>;
+def X28 : GP8<R28, "x28">, DwarfRegNum<[28]>;
+def X29 : GP8<R29, "x29">, DwarfRegNum<[29]>;
+def X30 : GP8<R30, "x30">, DwarfRegNum<[30]>;
+def X31 : GP8<R31, "x31">, DwarfRegNum<[31]>;
// Floating-point registers
def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
Modified: llvm/trunk/lib/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=47534&r1=47533&r2=47534&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Target.td (original)
+++ llvm/trunk/lib/Target/Target.td Sat Feb 23 18:56:13 2008
@@ -26,6 +26,7 @@
class Register<string n> {
string Namespace = "";
string Name = n;
+ string PrintableName = n;
// SpillSize - If this value is set to a non-zero value, it is the size in
// bits of the spill slot required to hold this register. If this value is
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=47534&r1=47533&r2=47534&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sat Feb 23 18:56:13 2008
@@ -512,7 +512,7 @@
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
@@ -524,6 +524,16 @@
OS << Reg.TheDef->getValueAsString("Name");
else
OS << Reg.getName();
+ OS << "\",\t\"";
+ if (!Reg.TheDef->getValueAsString("PrintableName").empty()) {
+ OS << Reg.TheDef->getValueAsString("PrintableName");
+ } else {
+ // Default to "name".
+ if (!Reg.TheDef->getValueAsString("Name").empty())
+ OS << Reg.TheDef->getValueAsString("Name");
+ else
+ OS << Reg.getName();
+ }
OS << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
OS << Reg.getName() << "_AliasSet,\t";
More information about the llvm-commits
mailing list