[llvm-commits] [llvm] r47467 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeTypesExpand.cpp

[Dan Gohman]

Author: djg
Date: Thu Feb 21 19:12:31 2008
New Revision: 47467

URL: http://llvm.org/viewvc/llvm-project?rev=47467&view=rev
Log:
Fix a regression in 403.gcc and 186.crafty introduced in 47383. To test
that a value is >= 32, check that all of the high bits are zero, not
just one or more.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47467&r1=47466&r2=47467&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 21 19:12:31 2008
@@ -5147,8 +5147,8 @@
   APInt KnownZero, KnownOne;
   DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
   
-  // If we know that the high bit of the shift amount is one, then we can do
-  // this as a couple of simple shifts.
+  // If we know that if any of the high bits of the shift amount are one, then
+  // we can do this as a couple of simple shifts.
   if (KnownOne.intersects(Mask)) {
     // Mask out the high bit, which we know is set.
     Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
@@ -5174,9 +5174,9 @@
     }
   }
   
-  // If we know that the high bit of the shift amount is zero, then we can do
-  // this as a couple of simple shifts.
-  if (KnownZero.intersects(Mask)) {
+  // If we know that the high bits of the shift amount are all zero, then we can
+  // do this as a couple of simple shifts.
+  if ((KnownZero & Mask) == Mask) {
     // Compute 32-amt.
     SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
                                  DAG.getConstant(NVTBits, Amt.getValueType()),

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=47467&r1=47466&r2=47467&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Thu Feb 21 19:12:31 2008
@@ -760,7 +760,7 @@
   APInt KnownZero, KnownOne;
   DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
   
-  // If we don't know anything about the high bit, exit.
+  // If we don't know anything about the high bits, exit.
   if (((KnownZero|KnownOne) & HighBitMask) == 0)
     return false;
 
@@ -768,8 +768,8 @@
   SDOperand InL, InH;
   GetExpandedOp(N->getOperand(0), InL, InH);
 
-  // If we know that the high bit of the shift amount is one, then we can do
-  // this as a couple of simple shifts.
+  // If we know that any of the high bits of the shift amount are one, then we
+  // can do this as a couple of simple shifts.
   if (KnownOne.intersects(HighBitMask)) {
     // Mask out the high bit, which we know is set.
     Amt = DAG.getNode(ISD::AND, ShTy, Amt,
@@ -793,27 +793,29 @@
     }
   }
   
-  // If we know that the high bit of the shift amount is zero, then we can do
-  // this as a couple of simple shifts.
-  assert(KnownZero.intersects(HighBitMask) && "Bad mask computation above");
-
-  // Compute 32-amt.
-  SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
-                               DAG.getConstant(NVTBits, ShTy),
-                               Amt);
-  unsigned Op1, Op2;
-  switch (N->getOpcode()) {
-  default: assert(0 && "Unknown shift");
-  case ISD::SHL:  Op1 = ISD::SHL; Op2 = ISD::SRL; break;
-  case ISD::SRL:
-  case ISD::SRA:  Op1 = ISD::SRL; Op2 = ISD::SHL; break;
-  }
+  // If we know that all of the high bits of the shift amount are zero, then we
+  // can do this as a couple of simple shifts.
+  if ((KnownZero & HighBitMask) == HighBitMask) {
+    // Compute 32-amt.
+    SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
+                                 DAG.getConstant(NVTBits, ShTy),
+                                 Amt);
+    unsigned Op1, Op2;
+    switch (N->getOpcode()) {
+    default: assert(0 && "Unknown shift");
+    case ISD::SHL:  Op1 = ISD::SHL; Op2 = ISD::SRL; break;
+    case ISD::SRL:
+    case ISD::SRA:  Op1 = ISD::SRL; Op2 = ISD::SHL; break;
+    }
     
-  Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
-  Hi = DAG.getNode(ISD::OR, NVT,
-                   DAG.getNode(Op1, NVT, InH, Amt),
-                   DAG.getNode(Op2, NVT, InL, Amt2));
-  return true;
+    Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
+    Hi = DAG.getNode(ISD::OR, NVT,
+                     DAG.getNode(Op1, NVT, InH, Amt),
+                     DAG.getNode(Op2, NVT, InL, Amt2));
+    return true;
+  }
+
+  return false;
 }