[llvm-commits] [llvm] r47375 - in /llvm/trunk: include/llvm/Assembly/Parser.h lib/AsmParser/llvmAsmParser.y lib/AsmParser/llvmAsmParser.y.cvs lib/CodeGen/RegAllocLinearScan.cpp lib/CodeGen/RegAllocLocal.cpp lib/Target/CellSPU/SPUFrameInfo.h lib/Target/CellSPU/SPURegisterInfo.cpp lib/Target/CellSPU/SPURegisterInfo.h lib/Target/X86/X86RegisterInfo.cpp lib/Transforms/Scalar/InstructionCombining.cpp lib/Transforms/Utils/LCSSA.cpp lib/VMCore/ParameterAttributes.cpp
Anton Korobeynikov
asl at math.spbu.ru
Wed Feb 20 04:08:02 PST 2008
Author: asl
Date: Wed Feb 20 06:07:57 2008
New Revision: 47375
URL: http://llvm.org/viewvc/llvm-project?rev=47375&view=rev
Log:
Fix newly-introduced 4.3 warnings
Modified:
llvm/trunk/include/llvm/Assembly/Parser.h
llvm/trunk/lib/AsmParser/llvmAsmParser.y
llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs
llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
llvm/trunk/lib/Transforms/Utils/LCSSA.cpp
llvm/trunk/lib/VMCore/ParameterAttributes.cpp
Modified: llvm/trunk/include/llvm/Assembly/Parser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Assembly/Parser.h?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Assembly/Parser.h (original)
+++ llvm/trunk/include/llvm/Assembly/Parser.h Wed Feb 20 06:07:57 2008
@@ -80,7 +80,7 @@
// ParserOptions in effect. If positional information is not applicable,
// these will return a value of -1.
//
- inline const void getErrorLocation(int &Line, int &Column) const {
+ inline void getErrorLocation(int &Line, int &Column) const {
Line = LineNo; Column = ColumnNo;
}
Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y Wed Feb 20 06:07:57 2008
@@ -578,12 +578,13 @@
} if (ID.Type == ValID::LocalName) {
std::string Name = ID.getName();
Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name);
- if (N)
+ if (N) {
if (N->getType()->getTypeID() == Type::LabelTyID)
BB = cast<BasicBlock>(N);
else
GenerateError("Reference to label '" + Name + "' is actually of type '"+
N->getType()->getDescription() + "'");
+ }
} else if (ID.Type == ValID::LocalID) {
if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) {
if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID)
Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs (original)
+++ llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Wed Feb 20 06:07:57 2008
@@ -578,12 +578,13 @@
} if (ID.Type == ValID::LocalName) {
std::string Name = ID.getName();
Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name);
- if (N)
+ if (N) {
if (N->getType()->getTypeID() == Type::LabelTyID)
BB = cast<BasicBlock>(N);
else
GenerateError("Reference to label '" + Name + "' is actually of type '"+
N->getType()->getDescription() + "'");
+ }
} else if (ID.Type == ValID::LocalID) {
if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) {
if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID)
Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Feb 20 06:07:57 2008
@@ -224,11 +224,12 @@
unsigned SrcReg, DstReg;
if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
return Reg;
- if (TargetRegisterInfo::isVirtualRegister(SrcReg))
+ if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
if (!vrm_->isAssignedReg(SrcReg))
return Reg;
else
SrcReg = vrm_->getPhys(SrcReg);
+ }
if (Reg == SrcReg)
return Reg;
@@ -864,7 +865,7 @@
// If copy coalescer has assigned a "preferred" register, check if it's
// available first.
- if (cur->preference)
+ if (cur->preference) {
if (prt_->isRegAvail(cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
@@ -872,6 +873,7 @@
} else
DOUT << "\t\tunable to assign the preferred register: "
<< tri_->getName(cur->preference) << "\n";
+ }
// Scan for the first available register.
TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Wed Feb 20 06:07:57 2008
@@ -775,11 +775,12 @@
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
- if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
if (unsigned VirtReg = PhysRegsUsed[i])
spillVirtReg(MBB, MI, VirtReg, i);
else
removePhysReg(i);
+ }
#if 0
// This checking code is very expensive.
Modified: llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h Wed Feb 20 06:07:57 2008
@@ -34,7 +34,7 @@
getCalleeSaveSpillSlots(unsigned &NumEntries) const;
//! Stack slot size (16 bytes)
- static const int stackSlotSize() {
+ static int stackSlotSize() {
return 16;
}
//! Maximum frame offset representable by a signed 10-bit integer
@@ -42,19 +42,19 @@
This is the maximum frame offset that can be expressed as a 10-bit
integer, used in D-form addresses.
*/
- static const int maxFrameOffset() {
+ static int maxFrameOffset() {
return ((1 << 9) - 1) * stackSlotSize();
}
//! Minimum frame offset representable by a signed 10-bit integer
- static const int minFrameOffset() {
+ static int minFrameOffset() {
return -(1 << 9) * stackSlotSize();
}
//! Minimum frame size (enough to spill LR + SP)
- static const int minStackSize() {
+ static int minStackSize() {
return (2 * stackSlotSize());
}
//! Frame size required to spill all registers plus frame info
- static const int fullSpillSize() {
+ static int fullSpillSize() {
return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
}
//! Number of instructions required to overcome hint-for-branch latency
@@ -65,7 +65,7 @@
of instructions occurs between the HBR and the target. Currently, HBRs
take 6 cycles, ergo, the magic number 6.
*/
- static const int branchHintPenalty() {
+ static int branchHintPenalty() {
return 6;
}
};
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Wed Feb 20 06:07:57 2008
@@ -221,7 +221,7 @@
return SPU_ArgRegs;
}
-const unsigned
+unsigned
SPURegisterInfo::getNumArgRegs()
{
return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Wed Feb 20 06:07:57 2008
@@ -90,7 +90,7 @@
static const unsigned *getArgRegs();
//! Return the size of the argument passing register array
- static const unsigned getNumArgRegs();
+ static unsigned getNumArgRegs();
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Feb 20 06:07:57 2008
@@ -145,11 +145,12 @@
const TargetRegisterClass *
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
- if (RC == &X86::CCRRegClass)
+ if (RC == &X86::CCRRegClass) {
if (Is64Bit)
return &X86::GR64RegClass;
else
return &X86::GR32RegClass;
+ }
return NULL;
}
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Wed Feb 20 06:07:57 2008
@@ -5481,8 +5481,8 @@
// Extending a relational comparison when we're checking the sign
// bit would not work.
if (Cast->hasOneUse() &&
- (ICI.isEquality() || AndCST->getValue().isNonNegative() &&
- RHSV.isNonNegative())) {
+ (ICI.isEquality() ||
+ (AndCST->getValue().isNonNegative() && RHSV.isNonNegative()))) {
uint32_t BitWidth =
cast<IntegerType>(Cast->getOperand(0)->getType())->getBitWidth();
APInt NewCST = AndCST->getValue();
Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Wed Feb 20 06:07:57 2008
@@ -90,7 +90,7 @@
std::map<DomTreeNode*, Value*> &Phis);
/// inLoop - returns true if the given block is within the current loop
- const bool inLoop(BasicBlock* B) {
+ bool inLoop(BasicBlock* B) {
return std::binary_search(LoopBlocks.begin(), LoopBlocks.end(), B);
}
};
Modified: llvm/trunk/lib/VMCore/ParameterAttributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ParameterAttributes.cpp?rev=47375&r1=47374&r2=47375&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ParameterAttributes.cpp (original)
+++ llvm/trunk/lib/VMCore/ParameterAttributes.cpp Wed Feb 20 06:07:57 2008
@@ -186,7 +186,7 @@
// For now, say we can't change a known alignment.
ParameterAttributes OldAlign = OldAttrs & ParamAttr::Alignment;
ParameterAttributes NewAlign = attrs & ParamAttr::Alignment;
- assert(!OldAlign || !NewAlign || OldAlign == NewAlign &&
+ assert((!OldAlign || !NewAlign || OldAlign == NewAlign) &&
"Attempt to change alignment!");
#endif
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