[llvm-commits] [llvm] r46587 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h
Evan Cheng
evan.cheng at apple.com
Thu Jan 31 00:02:33 PST 2008
How about changing it to FLT_ROUND (no s) or something else? Using a
trailing '_' seems silly.
Thanks,
Evan
On Jan 30, 2008, at 4:41 PM, Dan Gohman wrote:
> Author: djg
> Date: Wed Jan 30 18:41:03 2008
> New Revision: 46587
>
> URL: http://llvm.org/viewvc/llvm-project?rev=46587&view=rev
> Log:
> Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
> with the real FLT_ROUNDS (defined in <float.h>).
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 30
> 18:41:03 2008
> @@ -404,13 +404,13 @@
> /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't
> removed.
> FP_ROUND,
>
> - // FLT_ROUNDS - Returns current rounding mode:
> + // FLT_ROUNDS_ - Returns current rounding mode:
> // -1 Undefined
> // 0 Round to 0
> // 1 Round to nearest
> // 2 Round to +inf
> // 3 Round to -inf
> - FLT_ROUNDS,
> + FLT_ROUNDS_,
>
> /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP
> register, and
> /// rounds it to a floating point value. It then promotes it
> and returns it
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 30
> 18:41:03 2008
> @@ -3902,7 +3902,7 @@
> AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
> return Op.ResNo ? Tmp1 : Result;
> }
> - case ISD::FLT_ROUNDS: {
> + case ISD::FLT_ROUNDS_: {
> MVT::ValueType VT = Node->getValueType(0);
> switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
> default: assert(0 && "This action not supported for this op
> yet!");
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 30
> 18:41:03 2008
> @@ -3808,7 +3808,7 @@
> case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
> case ISD::TRUNCATE: return "truncate";
> case ISD::FP_ROUND: return "fp_round";
> - case ISD::FLT_ROUNDS: return "flt_rounds";
> + case ISD::FLT_ROUNDS_: return "flt_rounds";
> case ISD::FP_ROUND_INREG: return "fp_round_inreg";
> case ISD::FP_EXTEND: return "fp_extend";
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jan
> 30 18:41:03 2008
> @@ -2925,7 +2925,7 @@
> return 0;
>
> case Intrinsic::flt_rounds: {
> - setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
> + setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
> return 0;
> }
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Jan 30
> 18:41:03 2008
> @@ -111,7 +111,7 @@
> setOperationAction(ISD::FREM , MVT::f32, Expand);
> setOperationAction(ISD::FPOW , MVT::f32, Expand);
>
> - setOperationAction(ISD::FLT_ROUNDS, MVT::i32, Custom);
> + setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
>
> // If we're enabling GP optimizations, use hardware square root
> if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
> @@ -2215,7 +2215,7 @@
> return FP;
> }
>
> -static SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
> +static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
> /*
> The rounding mode is in bits 30:31 of FPSR, and has the following
> settings:
> @@ -3096,7 +3096,7 @@
> case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
> case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
> case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
> - case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
> + case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
>
> // Lower 64-bit shifts.
> case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jan 30
> 18:41:03 2008
> @@ -216,7 +216,7 @@
> setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
> setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
> setOperationAction(ISD::FREM , MVT::f64 , Expand);
> - setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
> + setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
>
> setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
> setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
> @@ -5048,7 +5048,7 @@
> }
> }
>
> -SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op,
> SelectionDAG &DAG) {
> +SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op,
> SelectionDAG &DAG) {
> /*
> The rounding mode is in bits 11:10 of FPSR, and has the following
> settings:
> @@ -5209,7 +5209,7 @@
> case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op,
> DAG);
> case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
> case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
> - case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
> + case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
> case ISD::CTLZ: return LowerCTLZ(Op, DAG);
> case ISD::CTTZ: return LowerCTTZ(Op, DAG);
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=46587&r1=46586&r2=46587&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jan 30 18:41:03
> 2008
> @@ -525,7 +525,7 @@
> SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG
> &DAG);
> SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
> SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
> - SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
> + SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
> SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
> SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
> SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
>
>
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