[llvm-commits] [llvm] r46538 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/PowerPC/
Dan Gohman
djg at cray.com
Tue Jan 29 16:15:11 PST 2008
Author: djg
Date: Tue Jan 29 18:15:11 2008
New Revision: 46538
URL: http://llvm.org/viewvc/llvm-project?rev=46538&view=rev
Log:
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/TargetSelectionDAG.td
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jan 29 18:15:11 2008
@@ -1477,6 +1477,12 @@
///
class LSBaseSDNode : public SDNode {
private:
+ // AddrMode - unindexed, pre-indexed, post-indexed.
+ ISD::MemIndexedMode AddrMode;
+
+ // MemoryVT - VT of in-memory value.
+ MVT::ValueType MemoryVT;
+
//! SrcValue - Memory location for alias analysis.
const Value *SrcValue;
@@ -1497,11 +1503,20 @@
*/
SDOperand Ops[4];
public:
- LSBaseSDNode(ISD::NodeType NodeTy, SDVTList VTs, const Value *SV, int SVO,
- unsigned Align, bool Vol)
+ LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned NumOperands,
+ SDVTList VTs, ISD::MemIndexedMode AM, MVT::ValueType VT,
+ const Value *SV, int SVO, unsigned Align, bool Vol)
: SDNode(NodeTy, VTs),
+ AddrMode(AM), MemoryVT(VT),
SrcValue(SV), SVOffset(SVO), Alignment(Align), IsVolatile(Vol)
- { }
+ {
+ for (unsigned i = 0; i != NumOperands; ++i)
+ Ops[i] = Operands[i];
+ InitOperands(Ops, NumOperands);
+ assert(Align != 0 && "Loads and stores should have non-zero aligment");
+ assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
+ "Only indexed loads and stores have a non-undef offset operand");
+ }
const SDOperand getChain() const {
return getOperand(0);
@@ -1520,10 +1535,22 @@
const Value *getSrcValue() const { return SrcValue; }
int getSrcValueOffset() const { return SVOffset; }
unsigned getAlignment() const { return Alignment; }
+ MVT::ValueType getMemoryVT() const { return MemoryVT; }
bool isVolatile() const { return IsVolatile; }
+ ISD::MemIndexedMode getAddressingMode() const { return AddrMode; }
+
+ /// isIndexed - Return true if this is a pre/post inc/dec load/store.
+ bool isIndexed() const { return AddrMode != ISD::UNINDEXED; }
+
+ /// isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
+ bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; }
+
static bool classof(const LSBaseSDNode *N) { return true; }
- static bool classof(const SDNode *N) { return true; }
+ static bool classof(const SDNode *N) {
+ return N->getOpcode() == ISD::LOAD ||
+ N->getOpcode() == ISD::STORE;
+ }
};
/// LoadSDNode - This class is used to represent ISD::LOAD nodes.
@@ -1531,41 +1558,20 @@
class LoadSDNode : public LSBaseSDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
- // AddrMode - unindexed, pre-indexed, post-indexed.
- ISD::MemIndexedMode AddrMode;
-
// ExtType - non-ext, anyext, sext, zext.
ISD::LoadExtType ExtType;
- // LoadedVT - VT of loaded value before extension.
- MVT::ValueType LoadedVT;
protected:
friend class SelectionDAG;
LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
- : LSBaseSDNode(ISD::LOAD, VTs, SV, O, Align, Vol),
- AddrMode(AM), ExtType(ETy), LoadedVT(LVT) {
- Ops[0] = ChainPtrOff[0]; // Chain
- Ops[1] = ChainPtrOff[1]; // Ptr
- Ops[2] = ChainPtrOff[2]; // Off
- InitOperands(Ops, 3);
- assert(Align != 0 && "Loads should have non-zero aligment");
- assert((getOffset().getOpcode() == ISD::UNDEF ||
- AddrMode != ISD::UNINDEXED) &&
- "Only indexed load has a non-undef offset operand");
- }
+ : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
+ VTs, AM, LVT, SV, O, Align, Vol),
+ ExtType(ETy) { }
public:
- ISD::MemIndexedMode getAddressingMode() const { return AddrMode; }
ISD::LoadExtType getExtensionType() const { return ExtType; }
- MVT::ValueType getLoadedVT() const { return LoadedVT; }
-
- /// isIndexed - Return true if this is a pre/post inc/dec load.
- bool isIndexed() const { return AddrMode != ISD::UNINDEXED; }
-
- /// isUnindexed - Return true if this is NOT a pre/post inc/dec load.
- bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; }
static bool classof(const LoadSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -1578,41 +1584,19 @@
class StoreSDNode : public LSBaseSDNode {
virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
- // AddrMode - unindexed, pre-indexed, post-indexed.
- ISD::MemIndexedMode AddrMode;
-
// IsTruncStore - True if the op does a truncation before store.
bool IsTruncStore;
-
- // StoredVT - VT of the value after truncation.
- MVT::ValueType StoredVT;
protected:
friend class SelectionDAG;
StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs,
ISD::MemIndexedMode AM, bool isTrunc, MVT::ValueType SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
- : LSBaseSDNode(ISD::STORE, VTs, SV, O, Align, Vol),
- AddrMode(AM), IsTruncStore(isTrunc), StoredVT(SVT) {
- Ops[0] = ChainValuePtrOff[0]; // Chain
- Ops[1] = ChainValuePtrOff[1]; // Value
- Ops[2] = ChainValuePtrOff[2]; // Ptr
- Ops[3] = ChainValuePtrOff[3]; // Off
- InitOperands(Ops, 4);
- assert(Align != 0 && "Stores should have non-zero aligment");
- assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
- "Only indexed store has a non-undef offset operand");
- }
+ : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
+ VTs, AM, SVT, SV, O, Align, Vol),
+ IsTruncStore(isTrunc) { }
public:
bool isTruncatingStore() const { return IsTruncStore; }
- MVT::ValueType getStoredVT() const { return StoredVT; }
- ISD::MemIndexedMode getAddressingMode() const { return AddrMode; }
-
- /// isIndexed - Return true if this is a pre/post inc/dec store.
- bool isIndexed() const { return AddrMode != ISD::UNINDEXED; }
-
- /// isUnindexed - Return true if this is NOT a pre/post inc/dec store.
- bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; }
static bool classof(const StoreSDNode *) { return true; }
static bool classof(const SDNode *N) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jan 29 18:15:11 2008
@@ -1655,7 +1655,7 @@
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadedVT();
+ MVT::ValueType EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1674,7 +1674,7 @@
if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadedVT();
+ MVT::ValueType EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@@ -1706,7 +1706,7 @@
else
EVT = MVT::Other;
- LoadedVT = LN0->getLoadedVT();
+ LoadedVT = LN0->getMemoryVT();
if (EVT != MVT::Other && LoadedVT > EVT &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
@@ -2744,7 +2744,7 @@
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadedVT();
+ MVT::ValueType EVT = LN0->getMemoryVT();
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
@@ -2861,7 +2861,7 @@
if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadedVT();
+ MVT::ValueType EVT = LN0->getMemoryVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
@@ -2958,7 +2958,7 @@
!ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getLoadedVT();
+ MVT::ValueType EVT = LN0->getMemoryVT();
SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
@@ -3154,7 +3154,7 @@
// fold (sext_inreg (extload x)) -> (sextload x)
if (ISD::isEXTLoad(N0.Val) &&
ISD::isUNINDEXEDLoad(N0.Val) &&
- EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
+ EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -3169,7 +3169,7 @@
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse() &&
- EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
+ EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@@ -3907,7 +3907,7 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
return false;
@@ -3915,7 +3915,7 @@
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
if (ST->isIndexed())
return false;
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
return false;
@@ -4034,7 +4034,7 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
return false;
@@ -4042,7 +4042,7 @@
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
if (ST->isIndexed())
return false;
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
!TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
return false;
@@ -4209,7 +4209,7 @@
if (Align > LD->getAlignment())
return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
Chain, Ptr, LD->getSrcValue(),
- LD->getSrcValueOffset(), LD->getLoadedVT(),
+ LD->getSrcValueOffset(), LD->getMemoryVT(),
LD->isVolatile(), Align);
}
}
@@ -4295,7 +4295,7 @@
LD->getValueType(0),
BetterChain, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset(),
- LD->getLoadedVT(),
+ LD->getMemoryVT(),
LD->isVolatile(),
LD->getAlignment());
}
@@ -4329,7 +4329,7 @@
if (unsigned Align = InferAlignment(Ptr, DAG)) {
if (Align > ST->getAlignment())
return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
- ST->getSrcValueOffset(), ST->getStoredVT(),
+ ST->getSrcValueOffset(), ST->getMemoryVT(),
ST->isVolatile(), Align);
}
}
@@ -4413,7 +4413,7 @@
if (ST->isTruncatingStore()) {
ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
ST->getSrcValue(),ST->getSrcValueOffset(),
- ST->getStoredVT(),
+ ST->getMemoryVT(),
ST->isVolatile(), ST->getAlignment());
} else {
ReplStore = DAG.getStore(BetterChain, Value, Ptr,
@@ -4441,23 +4441,23 @@
// only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
SDOperand Shorter =
- GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
+ GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT()));
AddToWorkList(Value.Val);
if (Shorter.Val)
return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
- ST->getSrcValueOffset(), ST->getStoredVT(),
+ ST->getSrcValueOffset(), ST->getMemoryVT(),
ST->isVolatile(), ST->getAlignment());
// Otherwise, see if we can simplify the operation with
// SimplifyDemandedBits, which only works if the value has a single use.
- if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
+ if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT())))
return SDOperand(N, 0);
}
// If this is a load followed by a store to the same location, then the store
// is dead/noop.
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
- if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() &&
+ if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
ST->isUnindexed() && !ST->isVolatile() &&
// There can't be any side effects between the load and store, such as
// a call or store.
@@ -4473,9 +4473,9 @@
&& TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
Value.Val->hasOneUse() && ST->isUnindexed() &&
TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
- ST->getStoredVT())) {
+ ST->getMemoryVT())) {
return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
- ST->getSrcValueOffset(), ST->getStoredVT(),
+ ST->getSrcValueOffset(), ST->getMemoryVT(),
ST->isVolatile(), ST->getAlignment());
}
@@ -4939,7 +4939,7 @@
LoadSDNode *RLD = cast<LoadSDNode>(RHS);
// If this is an EXTLOAD, the VT's must match.
- if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
+ if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
// FIXME: this conflates two src values, discarding one. This is not
// the right thing to do, but nothing uses srcvalues now. When they do,
// turn SrcValue into a list of locations.
@@ -4981,7 +4981,7 @@
TheSelect->getValueType(0),
LLD->getChain(), Addr, LLD->getSrcValue(),
LLD->getSrcValueOffset(),
- LLD->getLoadedVT(),
+ LLD->getMemoryVT(),
LLD->isVolatile(),
LLD->getAlignment());
}
@@ -5290,13 +5290,13 @@
const Value *&SrcValue, int &SrcValueOffset) {
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
+ Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3;
SrcValue = LD->getSrcValue();
SrcValueOffset = LD->getSrcValueOffset();
return true;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
- Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
+ Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3;
SrcValue = ST->getSrcValue();
SrcValueOffset = ST->getSrcValueOffset();
} else {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 29 18:15:11 2008
@@ -566,7 +566,7 @@
MVT::ValueType VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
- if (MVT::isFloatingPoint(ST->getStoredVT())) {
+ if (MVT::isFloatingPoint(ST->getMemoryVT())) {
// Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store.
MVT::ValueType intVT;
@@ -581,10 +581,10 @@
return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
SVOffset, ST->isVolatile(), Alignment);
}
- assert(MVT::isInteger(ST->getStoredVT()) &&
+ assert(MVT::isInteger(ST->getMemoryVT()) &&
"Unaligned store of unknown type.");
// Get the half-size VT
- MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
+ MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
int NumBits = MVT::getSizeInBits(NewStoredVT);
int IncrementSize = NumBits / 8;
@@ -616,7 +616,7 @@
SDOperand Chain = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
MVT::ValueType VT = LD->getValueType(0);
- MVT::ValueType LoadedVT = LD->getLoadedVT();
+ MVT::ValueType LoadedVT = LD->getMemoryVT();
if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
// Expand to a (misaligned) integer load of the same size,
// then bitconvert to floating point.
@@ -1781,7 +1781,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
+ getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
TLI);
@@ -1819,7 +1819,7 @@
AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3;
} else {
- MVT::ValueType SrcVT = LD->getLoadedVT();
+ MVT::ValueType SrcVT = LD->getMemoryVT();
unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -1960,7 +1960,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
+ getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
TLI);
@@ -2241,7 +2241,7 @@
}
}
- switch (getTypeAction(ST->getStoredVT())) {
+ switch (getTypeAction(ST->getMemoryVT())) {
case Legal: {
Tmp3 = LegalizeOp(ST->getValue());
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
@@ -2255,7 +2255,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
+ getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
TLI);
@@ -2280,7 +2280,7 @@
// Truncate the value and store the result.
Tmp3 = PromoteOp(ST->getValue());
Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
- SVOffset, ST->getStoredVT(),
+ SVOffset, ST->getMemoryVT(),
isVolatile, Alignment);
break;
@@ -2367,7 +2367,7 @@
SVOffset, MVT::i8, isVolatile, Alignment);
}
- MVT::ValueType StVT = ST->getStoredVT();
+ MVT::ValueType StVT = ST->getMemoryVT();
unsigned StWidth = MVT::getSizeInBits(StVT);
if (StWidth != MVT::getStoreSizeInBits(StVT)) {
@@ -2442,7 +2442,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
+ getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
TLI);
@@ -4294,7 +4294,7 @@
Result = DAG.getExtLoad(ExtType, NVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
- LD->getLoadedVT(),
+ LD->getMemoryVT(),
LD->isVolatile(),
LD->getAlignment());
// Remember that we legalized the chain.
@@ -5767,7 +5767,7 @@
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
} else {
- MVT::ValueType EVT = LD->getLoadedVT();
+ MVT::ValueType EVT = LD->getMemoryVT();
if ((VT == MVT::f64 && EVT == MVT::f32) ||
(VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Tue Jan 29 18:15:11 2008
@@ -265,8 +265,8 @@
// Handle endianness of the load.
if (!TLI.isLittleEndian())
std::swap(Lo, Hi);
- } else if (MVT::getSizeInBits(N->getLoadedVT()) <= MVT::getSizeInBits(NVT)) {
- MVT::ValueType EVT = N->getLoadedVT();
+ } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
+ MVT::ValueType EVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
isVolatile, Alignment);
@@ -294,7 +294,7 @@
isVolatile, Alignment);
unsigned ExcessBits =
- MVT::getSizeInBits(N->getLoadedVT()) - MVT::getSizeInBits(NVT);
+ MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
// Increment the pointer to the other half.
@@ -312,7 +312,7 @@
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// the cost of some bit-fiddling.
- MVT::ValueType EVT = N->getLoadedVT();
+ MVT::ValueType EVT = N->getMemoryVT();
unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
@@ -1058,10 +1058,10 @@
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
- } else if (MVT::getSizeInBits(N->getStoredVT()) <= MVT::getSizeInBits(NVT)) {
+ } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
GetExpandedOp(N->getValue(), Lo, Hi);
return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
- N->getStoredVT(), isVolatile, Alignment);
+ N->getMemoryVT(), isVolatile, Alignment);
} else if (TLI.isLittleEndian()) {
// Little-endian - low bits are at low addresses.
GetExpandedOp(N->getValue(), Lo, Hi);
@@ -1070,7 +1070,7 @@
isVolatile, Alignment);
unsigned ExcessBits =
- MVT::getSizeInBits(N->getStoredVT()) - MVT::getSizeInBits(NVT);
+ MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
// Increment the pointer to the other half.
@@ -1086,7 +1086,7 @@
// the cost of some bit-fiddling.
GetExpandedOp(N->getValue(), Lo, Hi);
- MVT::ValueType EVT = N->getStoredVT();
+ MVT::ValueType EVT = N->getMemoryVT();
unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp Tue Jan 29 18:15:11 2008
@@ -188,7 +188,7 @@
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
- N->getLoadedVT(), N->isVolatile(),
+ N->getMemoryVT(), N->isVolatile(),
N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
@@ -486,6 +486,6 @@
// Truncate the value and store the result.
return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
- SVOffset, N->getStoredVT(),
+ SVOffset, N->getMemoryVT(),
isVolatile, Alignment);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jan 29 18:15:11 2008
@@ -371,7 +371,7 @@
LoadSDNode *LD = cast<LoadSDNode>(N);
ID.AddInteger(LD->getAddressingMode());
ID.AddInteger(LD->getExtensionType());
- ID.AddInteger((unsigned int)(LD->getLoadedVT()));
+ ID.AddInteger((unsigned int)(LD->getMemoryVT()));
ID.AddInteger(LD->getAlignment());
ID.AddInteger(LD->isVolatile());
break;
@@ -380,7 +380,7 @@
StoreSDNode *ST = cast<StoreSDNode>(N);
ID.AddInteger(ST->getAddressingMode());
ID.AddInteger(ST->isTruncatingStore());
- ID.AddInteger((unsigned int)(ST->getStoredVT()));
+ ID.AddInteger((unsigned int)(ST->getMemoryVT()));
ID.AddInteger(ST->getAlignment());
ID.AddInteger(ST->isVolatile());
break;
@@ -634,13 +634,13 @@
if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
ID.AddInteger(LD->getAddressingMode());
ID.AddInteger(LD->getExtensionType());
- ID.AddInteger((unsigned int)(LD->getLoadedVT()));
+ ID.AddInteger((unsigned int)(LD->getMemoryVT()));
ID.AddInteger(LD->getAlignment());
ID.AddInteger(LD->isVolatile());
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ID.AddInteger(ST->getAddressingMode());
ID.AddInteger(ST->isTruncatingStore());
- ID.AddInteger((unsigned int)(ST->getStoredVT()));
+ ID.AddInteger((unsigned int)(ST->getMemoryVT()));
ID.AddInteger(ST->getAlignment());
ID.AddInteger(ST->isVolatile());
}
@@ -1264,7 +1264,7 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT::ValueType VT = LD->getLoadedVT();
+ MVT::ValueType VT = LD->getMemoryVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
}
return;
@@ -1561,10 +1561,10 @@
switch (ExtType) {
default: break;
case ISD::SEXTLOAD: // '17' bits known
- Tmp = MVT::getSizeInBits(LD->getLoadedVT());
+ Tmp = MVT::getSizeInBits(LD->getMemoryVT());
return VTBits-Tmp+1;
case ISD::ZEXTLOAD: // '16' bits known
- Tmp = MVT::getSizeInBits(LD->getLoadedVT());
+ Tmp = MVT::getSizeInBits(LD->getMemoryVT());
return VTBits-Tmp;
}
}
@@ -2391,14 +2391,14 @@
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
ID.AddInteger(AM);
ID.AddInteger(LD->getExtensionType());
- ID.AddInteger((unsigned int)(LD->getLoadedVT()));
+ ID.AddInteger((unsigned int)(LD->getMemoryVT()));
ID.AddInteger(LD->getAlignment());
ID.AddInteger(LD->isVolatile());
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new LoadSDNode(Ops, VTs, AM,
- LD->getExtensionType(), LD->getLoadedVT(),
+ LD->getExtensionType(), LD->getMemoryVT(),
LD->getSrcValue(), LD->getSrcValueOffset(),
LD->getAlignment(), LD->isVolatile());
CSEMap.InsertNode(N, IP);
@@ -2501,14 +2501,14 @@
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(AM);
ID.AddInteger(ST->isTruncatingStore());
- ID.AddInteger((unsigned int)(ST->getStoredVT()));
+ ID.AddInteger((unsigned int)(ST->getMemoryVT()));
ID.AddInteger(ST->getAlignment());
ID.AddInteger(ST->isVolatile());
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
SDNode *N = new StoreSDNode(Ops, VTs, AM,
- ST->isTruncatingStore(), ST->getStoredVT(),
+ ST->isTruncatingStore(), ST->getMemoryVT(),
ST->getSrcValue(), ST->getSrcValueOffset(),
ST->getAlignment(), ST->isVolatile());
CSEMap.InsertNode(N, IP);
@@ -3966,7 +3966,7 @@
break;
}
if (doExt)
- cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
+ cerr << MVT::getValueTypeString(LD->getMemoryVT()) << ">";
const char *AM = getIndexedModeName(LD->getAddressingMode());
if (*AM)
@@ -3986,7 +3986,7 @@
if (ST->isTruncatingStore())
cerr << " <trunc "
- << MVT::getValueTypeString(ST->getStoredVT()) << ">";
+ << MVT::getValueTypeString(ST->getMemoryVT()) << ">";
const char *AM = getIndexedModeName(ST->getAddressingMode());
if (*AM)
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Tue Jan 29 18:15:11 2008
@@ -164,7 +164,7 @@
break;
}
if (doExt)
- Op += MVT::getValueTypeString(LD->getLoadedVT()) + ">";
+ Op += MVT::getValueTypeString(LD->getMemoryVT()) + ">";
if (LD->isVolatile())
Op += "<V>";
Op += LD->getIndexedModeName(LD->getAddressingMode());
@@ -172,7 +172,7 @@
Op += " A=" + utostr(LD->getAlignment());
} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Node)) {
if (ST->isTruncatingStore())
- Op += "<trunc " + MVT::getValueTypeString(ST->getStoredVT()) + ">";
+ Op += "<trunc " + MVT::getValueTypeString(ST->getMemoryVT()) + ">";
if (ST->isVolatile())
Op += "<V>";
Op += ST->getIndexedModeName(ST->getAddressingMode());
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Jan 29 18:15:11 2008
@@ -842,7 +842,7 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT::ValueType VT = LD->getLoadedVT();
+ MVT::ValueType VT = LD->getMemoryVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
}
break;
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jan 29 18:15:11 2008
@@ -659,7 +659,7 @@
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Op);
ISD::MemIndexedMode AM = LD->getAddressingMode();
- MVT::ValueType LoadedVT = LD->getLoadedVT();
+ MVT::ValueType LoadedVT = LD->getMemoryVT();
if (AM != ISD::UNINDEXED) {
SDOperand Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jan 29 18:15:11 2008
@@ -1729,11 +1729,11 @@
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
} else
return false;
@@ -1762,10 +1762,10 @@
SDOperand Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
} else
return false;
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Jan 29 18:15:11 2008
@@ -542,7 +542,7 @@
LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDOperand the_chain = LN->getChain();
- MVT::ValueType VT = LN->getLoadedVT();
+ MVT::ValueType VT = LN->getMemoryVT();
MVT::ValueType OpVT = Op.Val->getValueType(0);
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
@@ -652,7 +652,7 @@
StoreSDNode *SN = cast<StoreSDNode>(Op);
SDOperand Value = SN->getValue();
MVT::ValueType VT = Value.getValueType();
- MVT::ValueType StVT = (!SN->isTruncatingStore() ? VT : SN->getStoredVT());
+ MVT::ValueType StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
unsigned alignment = SN->getAlignment();
Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jan 29 18:15:11 2008
@@ -466,7 +466,7 @@
AddToISelQueue(Chain);
AddToISelQueue(Address);
- MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
+ MVT::ValueType TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default:
@@ -528,7 +528,7 @@
case MVT::f64: Opc = IA64::STF8; break;
}
} else { // Truncating store
- switch(ST->getStoredVT()) {
+ switch(ST->getMemoryVT()) {
default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Jan 29 18:15:11 2008
@@ -921,7 +921,7 @@
case ISD::LOAD: {
// Handle preincrement loads.
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT::ValueType LoadedVT = LD->getLoadedVT();
+ MVT::ValueType LoadedVT = LD->getMemoryVT();
// Normal loads are handled by code generated from the .td file.
if (LD->getAddressingMode() != ISD::PRE_INC)
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jan 29 18:15:11 2008
@@ -963,12 +963,12 @@
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ST = ST;
Ptr = ST->getBasePtr();
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
} else
return false;
@@ -992,7 +992,7 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
// sext i32 to i64 when addr mode is r+i.
- if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
+ if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
LD->getExtensionType() == ISD::SEXTLOAD &&
isa<ConstantSDNode>(Offset))
return false;
Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=46538&r1=46537&r2=46538&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/lib/Target/TargetSelectionDAG.td Tue Jan 29 18:15:11 2008
@@ -444,42 +444,42 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getMemoryVT() == MVT::i1;
return false;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getMemoryVT() == MVT::i8;
return false;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getMemoryVT() == MVT::i16;
return false;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getMemoryVT() == MVT::i32;
return false;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::f32;
+ LD->getMemoryVT() == MVT::f32;
return false;
}]>;
def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::EXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::f64;
+ LD->getMemoryVT() == MVT::f64;
return false;
}]>;
@@ -487,28 +487,28 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getMemoryVT() == MVT::i1;
return false;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getMemoryVT() == MVT::i8;
return false;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getMemoryVT() == MVT::i16;
return false;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::SEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getMemoryVT() == MVT::i32;
return false;
}]>;
@@ -516,28 +516,28 @@
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i1;
+ LD->getMemoryVT() == MVT::i1;
return false;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i8;
+ LD->getMemoryVT() == MVT::i8;
return false;
}]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i16;
+ LD->getMemoryVT() == MVT::i16;
return false;
}]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
return LD->getExtensionType() == ISD::ZEXTLOAD &&
LD->getAddressingMode() == ISD::UNINDEXED &&
- LD->getLoadedVT() == MVT::i32;
+ LD->getMemoryVT() == MVT::i32;
return false;
}]>;
@@ -554,35 +554,35 @@
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
- return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
+ return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
- return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
+ return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
- return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
+ return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
- return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
+ return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
- return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f64 &&
+ return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
@@ -603,7 +603,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
}
return false;
}]>;
@@ -612,7 +612,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
}
return false;
}]>;
@@ -621,7 +621,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
}
return false;
}]>;
@@ -630,7 +630,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
}
return false;
}]>;
@@ -639,7 +639,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
}
return false;
}]>;
@@ -659,7 +659,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
}
return false;
}]>;
@@ -668,7 +668,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
}
return false;
}]>;
@@ -677,7 +677,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
}
return false;
}]>;
@@ -686,7 +686,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
}
return false;
}]>;
@@ -695,7 +695,7 @@
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ISD::MemIndexedMode AM = ST->getAddressingMode();
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
- ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
+ ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
}
return false;
}]>;
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