[llvm-commits] [llvm] r46177 - in /llvm/branches/Apple/llvmCore-2010: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/CodeGen/X86/

Devang Patel dpatel at apple.com
Fri Jan 18 12:09:10 PST 2008


Author: dpatel
Date: Fri Jan 18 14:09:08 2008
New Revision: 46177

URL: http://llvm.org/viewvc/llvm-project?rev=46177&view=rev
Log:
Revert r46140 and r46125

Modified:
    llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAG.h
    llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAGNodes.h
    llvm/branches/Apple/llvmCore-2010/include/llvm/Target/TargetLowering.h
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrInfo.td
    llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrThumb.td
    llvm/branches/Apple/llvmCore-2010/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/IA64/IA64ISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsInstrInfo.td
    llvm/branches/Apple/llvmCore-2010/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/Sparc/SparcInstrInfo.td
    llvm/branches/Apple/llvmCore-2010/lib/Target/TargetSelectionDAG.td
    llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86InstrInfo.td
    llvm/branches/Apple/llvmCore-2010/test/CodeGen/X86/storetrunc-fp.ll

Modified: llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAG.h?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAG.h Fri Jan 18 14:09:08 2008
@@ -177,7 +177,6 @@
   //
   SDOperand getString(const std::string &Val);
   SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false);
-  SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
   SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) {
     return getConstant(Val, VT, true);
   }

Modified: llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/Apple/llvmCore-2010/include/llvm/CodeGen/SelectionDAGNodes.h Fri Jan 18 14:09:08 2008
@@ -385,24 +385,15 @@
     // operand, a ValueType node.
     SIGN_EXTEND_INREG,
 
-    /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
-    /// integer.
+    // FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
+    // integer.
     FP_TO_SINT,
     FP_TO_UINT,
 
-    /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
-    /// down to the precision of the destination VT.  TRUNC is a flag, which is
-    /// always an integer that is zero or one.  If TRUNC is 0, this is a
-    /// normal rounding, if it is 1, this FP_ROUND is known to not change the
-    /// value of Y.
-    ///
-    /// The TRUNC = 1 case is used in cases where we know that the value will
-    /// not be modified by the node, because Y is not using any of the extra
-    /// precision of source type.  This allows certain transformations like
-    /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 
-    /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
+    // FP_ROUND - Perform a rounding operation from the current
+    // precision down to the specified precision (currently always 64->32).
     FP_ROUND,
-    
+
     // FLT_ROUNDS - Returns current rounding mode:
     // -1 Undefined
     //  0 Round to 0
@@ -411,14 +402,14 @@
     //  3 Round to -inf
     FLT_ROUNDS,
 
-    /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
-    /// rounds it to a floating point value.  It then promotes it and returns it
-    /// in a register of the same size.  This operation effectively just
-    /// discards excess precision.  The type to round down to is specified by
-    /// the VT operand, a VTSDNode.
+    // FP_ROUND_INREG - This operator takes a floating point register, and
+    // rounds it to a floating point value.  It then promotes it and returns it
+    // in a register of the same size.  This operation effectively just discards
+    // excess precision.  The type to round down to is specified by the 1th
+    // operation, a VTSDNode (currently always 64->32->64).
     FP_ROUND_INREG,
 
-    /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
+    // FP_EXTEND - Extend a smaller FP type into a larger FP type.
     FP_EXTEND,
 
     // BIT_CONVERT - Theis operator converts between integer and FP values, as

Modified: llvm/branches/Apple/llvmCore-2010/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/include/llvm/Target/TargetLowering.h?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/Apple/llvmCore-2010/include/llvm/Target/TargetLowering.h Fri Jan 18 14:09:08 2008
@@ -301,22 +301,19 @@
            getLoadXAction(LType, VT) == Custom;
   }
   
-  /// getTruncStoreAction - Return how this store with truncation should be
-  /// treated: either it is legal, needs to be promoted to a larger size, needs
-  /// to be expanded to some other code sequence, or the target has a custom
-  /// expander for it.
-  LegalizeAction getTruncStoreAction(MVT::ValueType ValVT, 
-                                     MVT::ValueType MemVT) const {
-    assert(ValVT < MVT::LAST_VALUETYPE && MemVT < 32 && 
-           "Table isn't big enough!");
-    return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3);
+  /// getStoreXAction - Return how this store with truncation should be treated:
+  /// either it is legal, needs to be promoted to a larger size, needs to be
+  /// expanded to some other code sequence, or the target has a custom expander
+  /// for it.
+  LegalizeAction getStoreXAction(MVT::ValueType VT) const {
+    if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
+    return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
   }
   
-  /// isTruncStoreLegal - Return true if the specified store with truncation is
+  /// isStoreXLegal - Return true if the specified store with truncation is
   /// legal on this target.
-  bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const {
-    return getTruncStoreAction(ValVT, MemVT) == Legal ||
-           getTruncStoreAction(ValVT, MemVT) == Custom;
+  bool isStoreXLegal(MVT::ValueType VT) const {
+    return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
   }
 
   /// getIndexedLoadAction - Return how the indexed load should be treated:
@@ -763,14 +760,12 @@
     LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
   }
   
-  /// setTruncStoreAction - Indicate that the specified truncating store does
+  /// setStoreXAction - Indicate that the specified store with truncation does
   /// not work with the with specified type and indicate what to do about it.
-  void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT,
-                           LegalizeAction Action) {
-    assert(ValVT < MVT::LAST_VALUETYPE && MemVT < 32 && 
-           "Table isn't big enough!");
-    TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
-    TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
+  void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
+    assert(VT < 32 && "Table isn't big enough!");
+    StoreXActions &= ~(uint64_t(3UL) << VT*2);
+    StoreXActions |= (uint64_t)Action << VT*2;
   }
 
   /// setIndexedLoadAction - Indicate that the specified indexed load does or
@@ -1188,9 +1183,10 @@
   /// with the load.
   uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
   
-  /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
-  /// indicates how instruction selection should deal with the store.
-  uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
+  /// StoreXActions - For each store with truncation of each value type, keep a
+  /// LegalizeAction that indicates how instruction selection should deal with
+  /// the store.
+  uint64_t StoreXActions;
 
   /// IndexedModeActions - For each indexed mode and each value type, keep a
   /// pair of LegalizeAction that indicates how instruction selection should

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jan 18 14:09:08 2008
@@ -135,7 +135,6 @@
       SDOperand To[] = { Res0, Res1 };
       return CombineTo(N, To, 2, AddTo);
     }
-    
   private:    
     
     /// SimplifyDemandedBits - Check the specified integer node value to see if
@@ -461,13 +460,10 @@
                        GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
     
   case ISD::FP_EXTEND:
+  case ISD::FP_ROUND:
   case ISD::FSIN:
     return DAG.getNode(Op.getOpcode(), Op.getValueType(),
                        GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
-  case ISD::FP_ROUND:
-      return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
-                         GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
-                         Op.getOperand(1));
   }
 }
 
@@ -1690,7 +1686,8 @@
   if (N1C && N0.getOpcode() == ISD::LOAD) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     if (LN0->getExtensionType() != ISD::SEXTLOAD &&
-        LN0->isUnindexed() && N0.hasOneUse()) {
+        LN0->getAddressingMode() == ISD::UNINDEXED &&
+        N0.hasOneUse()) {
       MVT::ValueType EVT, LoadedVT;
       if (N1C->getValue() == 255)
         EVT = MVT::i8;
@@ -3636,13 +3633,12 @@
 
 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
-  SDOperand N1 = N->getOperand(1);
   ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
   MVT::ValueType VT = N->getValueType(0);
   
   // fold (fp_round c1fp) -> c1fp
   if (N0CFP && N0.getValueType() != MVT::ppcf128)
-    return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
+    return DAG.getNode(ISD::FP_ROUND, VT, N0);
   
   // fold (fp_round (fp_extend x)) -> x
   if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
@@ -3650,7 +3646,7 @@
   
   // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
   if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
-    SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
+    SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
     AddToWorkList(Tmp.Val);
     return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
   }
@@ -3680,22 +3676,12 @@
   // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
   if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND)
     return SDOperand();
-
+  
   // fold (fp_extend c1fp) -> c1fp
   if (N0CFP && VT != MVT::ppcf128)
     return DAG.getNode(ISD::FP_EXTEND, VT, N0);
-
-  // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
-  // value of X.
-  if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
-    SDOperand In = N0.getOperand(0);
-    if (In.getValueType() == VT) return In;
-    if (VT < In.getValueType())
-      return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
-    return DAG.getNode(ISD::FP_EXTEND, VT, In);
-  }
-      
-  // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
+  
+  // fold (fpext (load x)) -> (fpext (fpround (extload x)))
   if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
       (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
@@ -3706,8 +3692,7 @@
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
-                                  DAG.getIntPtrConstant(1)),
+    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
               ExtLoad.getValue(1));
     return SDOperand(N, 0);   // Return N so it doesn't get rechecked!
   }
@@ -3809,7 +3794,7 @@
   SDOperand Ptr;
   MVT::ValueType VT;
   if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
-    if (LD->isIndexed())
+    if (LD->getAddressingMode() != ISD::UNINDEXED)
       return false;
     VT = LD->getLoadedVT();
     if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
@@ -3817,7 +3802,7 @@
       return false;
     Ptr = LD->getBasePtr();
   } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
-    if (ST->isIndexed())
+    if (ST->getAddressingMode() != ISD::UNINDEXED)
       return false;
     VT = ST->getStoredVT();
     if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
@@ -3936,7 +3921,7 @@
   SDOperand Ptr;
   MVT::ValueType VT;
   if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
-    if (LD->isIndexed())
+    if (LD->getAddressingMode() != ISD::UNINDEXED)
       return false;
     VT = LD->getLoadedVT();
     if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
@@ -3944,7 +3929,7 @@
       return false;
     Ptr = LD->getBasePtr();
   } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
-    if (ST->isIndexed())
+    if (ST->getAddressingMode() != ISD::UNINDEXED)
       return false;
     VT = ST->getStoredVT();
     if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
@@ -4186,7 +4171,7 @@
   // If this is a store of a bit convert, store the input value if the
   // resultant store does not need a higher alignment than the original.
   if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
-      ST->isUnindexed()) {
+      ST->getAddressingMode() == ISD::UNINDEXED) {
     unsigned Align = ST->getAlignment();
     MVT::ValueType SVT = Value.getOperand(0).getValueType();
     unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
@@ -4284,7 +4269,7 @@
     return SDOperand(N, 0);
 
   // FIXME: is there such a thing as a truncating indexed store?
-  if (ST->isTruncatingStore() && ST->isUnindexed() &&
+  if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED &&
       MVT::isInteger(Value.getValueType())) {
     // See if we can simplify the input to this truncstore with knowledge that
     // only the low bits are being used.  For example:
@@ -4307,7 +4292,8 @@
   // is dead/noop.
   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
     if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() &&
-        ST->isUnindexed() && !ST->isVolatile() &&
+        ST->getAddressingMode() == ISD::UNINDEXED &&
+        !ST->isVolatile() &&
         // There can't be any side effects between the load and store, such as
         // a call or store.
         Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
@@ -4316,18 +4302,6 @@
     }
   }
   
-  // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
-  // truncating store.  We can do this even if this is already a truncstore.
-  if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
-      && TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
-      Value.Val->hasOneUse() && ST->isUnindexed() &&
-      TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
-                            ST->getStoredVT())) {
-    return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
-                             ST->getSrcValueOffset(), ST->getStoredVT(),
-                             ST->isVolatile(), ST->getAlignment());
-  }
-  
   return SDOperand();
 }
 
@@ -4463,11 +4437,13 @@
 
       // Otherwise, use InIdx + VecSize
       unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
-      BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
+      BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
+                                                TLI.getPointerTy()));
     }
     
     // Add count and size info.
-    MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
+    MVT::ValueType BuildVecVT =
+      MVT::getVectorType(TLI.getPointerTy(), NumElts);
     
     // Return the new VECTOR_SHUFFLE node.
     SDOperand Ops[5];

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 18 14:09:08 2008
@@ -220,6 +220,10 @@
 
   SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
   SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
+  
+  SDOperand getIntPtrConstant(uint64_t Val) {
+    return DAG.getConstant(Val, TLI.getPointerTy());
+  }
 };
 }
 
@@ -2119,7 +2123,7 @@
             Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
                               SVOffset, isVolatile, Alignment);
             Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
-                               DAG.getIntPtrConstant(4));
+                               getIntPtrConstant(4));
             Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
                               isVolatile, MinAlign(Alignment, 4U));
 
@@ -2182,9 +2186,8 @@
         if (MVT::isVector(ST->getValue().getValueType())) {
           SDNode *InVal = ST->getValue().Val;
           int InIx = ST->getValue().ResNo;
-          MVT::ValueType InVT = InVal->getValueType(InIx);
-          unsigned NumElems = MVT::getVectorNumElements(InVT);
-          MVT::ValueType EVT = MVT::getVectorElementType(InVT);
+          unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
+          MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
 
           // Figure out if there is a simple type corresponding to this Vector
           // type.  If so, convert to the vector type.
@@ -2228,7 +2231,7 @@
         }
 
         Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
-                           DAG.getIntPtrConstant(IncrementSize));
+                           getIntPtrConstant(IncrementSize));
         assert(isTypeLegal(Tmp2.getValueType()) &&
                "Pointers must be legal!");
         SVOffset += IncrementSize;
@@ -2239,24 +2242,15 @@
         break;
       }
     } else {
-      switch (getTypeAction(ST->getValue().getValueType())) {
-      case Legal:
-        Tmp3 = LegalizeOp(ST->getValue());
-        break;
-      case Promote:
-        // We can promote the value, the truncstore will still take care of it.
-        Tmp3 = PromoteOp(ST->getValue());
-        break;
-      case Expand:
-        // Just store the low part.  This may become a non-trunc store, so make
-        // sure to use getTruncStore, not UpdateNodeOperands below.
-        ExpandOp(ST->getValue(), Tmp3, Tmp4);
-        return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
-                                 SVOffset, MVT::i8, isVolatile, Alignment);
-      }
-    
-      // Unconditionally promote TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
-      if (ST->getStoredVT() == MVT::i1) {
+      // Truncating store
+      assert(isTypeLegal(ST->getValue().getValueType()) &&
+             "Cannot handle illegal TRUNCSTORE yet!");
+      Tmp3 = LegalizeOp(ST->getValue());
+    
+      // The only promote case we handle is TRUNCSTORE:i1 X into
+      //   -> TRUNCSTORE:i8 (and X, 1)
+      if (ST->getStoredVT() == MVT::i1 &&
+          TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
         // Promote the bool to a mask then store.
         Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
                            DAG.getConstant(1, Tmp3.getValueType()));
@@ -2270,7 +2264,7 @@
       }
 
       MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
-      switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
+      switch (TLI.getStoreXAction(StVT)) {
       default: assert(0 && "This action is not supported yet!");
       case TargetLowering::Legal:
         // If this is an unaligned store and the target doesn't support it,
@@ -2284,7 +2278,8 @@
         }
         break;
       case TargetLowering::Custom:
-        Result = TLI.LowerOperation(Result, DAG);
+        Tmp1 = TLI.LowerOperation(Result, DAG);
+        if (Tmp1.Val) Result = Tmp1;
         break;
       }
     }
@@ -2434,11 +2429,7 @@
       Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
       // Perform the larger operation, then round down.
       Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
-      if (TruncOp != ISD::FP_ROUND)
-        Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
-      else
-        Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
-                             DAG.getIntPtrConstant(0));
+      Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
       break;
     }
     }
@@ -3505,13 +3496,13 @@
       MVT::ValueType OVT = Node->getOperand(0).getValueType();
       // Convert ppcf128 to i32
       if (OVT == MVT::ppcf128 && VT == MVT::i32) {
-        if (Node->getOpcode() == ISD::FP_TO_SINT) {
-          Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 
-                               Node->getOperand(0), DAG.getValueType(MVT::f64));
-          Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 
-                               DAG.getIntPtrConstant(1));
-          Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
-        } else {
+        if (Node->getOpcode()==ISD::FP_TO_SINT)
+          Result = DAG.getNode(ISD::FP_TO_SINT, VT,
+                             DAG.getNode(ISD::FP_ROUND, MVT::f64,
+                                         (DAG.getNode(ISD::FP_ROUND_INREG, 
+                                          MVT::ppcf128, Node->getOperand(0),
+                                          DAG.getValueType(MVT::f64)))));
+        else {
           const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
           APFloat apf = APFloat(APInt(128, 2, TwoE31));
           Tmp2 = DAG.getConstantFP(apf, OVT);
@@ -3582,13 +3573,14 @@
     break;
 
   case ISD::FP_EXTEND: {
-    MVT::ValueType DstVT = Op.getValueType();
-    MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
-    if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
-      // The only other way we can lower this is to turn it into a STORE,
-      // LOAD pair, targetting a temporary location (a stack slot).
-      Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
-      break;
+      MVT::ValueType DstVT = Op.getValueType();
+      MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+      if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
+        // The only other way we can lower this is to turn it into a STORE,
+        // LOAD pair, targetting a temporary location (a stack slot).
+        Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
+        break;
+      }
     }
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
     case Expand: assert(0 && "Shouldn't need to expand other operators here!");
@@ -3602,37 +3594,35 @@
       break;
     }
     break;
-  }
   case ISD::FP_ROUND: {
-    MVT::ValueType DstVT = Op.getValueType();
-    MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
-    if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
-      if (SrcVT == MVT::ppcf128) {
-        SDOperand Lo, Hi;
-        ExpandOp(Node->getOperand(0), Lo, Hi);
-        // Round it the rest of the way (e.g. to f32) if needed.
-        Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1));
-        break;
+      MVT::ValueType DstVT = Op.getValueType();
+      MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+      if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
+        if (SrcVT == MVT::ppcf128) {
+          SDOperand Lo, Hi;
+          ExpandOp(Node->getOperand(0), Lo, Hi);
+          Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi);
+          break;
+        } else {
+          // The only other way we can lower this is to turn it into a STORE,
+          // LOAD pair, targetting a temporary location (a stack slot).
+          Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
+          break;
+        }
       }
-      // The only other way we can lower this is to turn it into a STORE,
-      // LOAD pair, targetting a temporary location (a stack slot).
-      Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
-      break;
     }
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
     case Expand: assert(0 && "Shouldn't need to expand other operators here!");
     case Legal:
       Tmp1 = LegalizeOp(Node->getOperand(0));
-      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1);
       break;
     case Promote:
       Tmp1 = PromoteOp(Node->getOperand(0));
-      Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
-                           Node->getOperand(1));
+      Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1);
       break;
     }
     break;
-  }
   case ISD::ANY_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::SIGN_EXTEND:
@@ -3879,18 +3869,13 @@
     case Expand: assert(0 && "BUG: Cannot expand FP regs!");
     case Promote:  assert(0 && "Unreachable with 2 FP types!");
     case Legal:
-      if (Node->getConstantOperandVal(1) == 0) {
-        // Input is legal?  Do an FP_ROUND_INREG.
-        Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
-                             DAG.getValueType(VT));
-      } else {
-        // Just remove the truncate, it isn't affecting the value.
-        Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 
-                             Node->getOperand(1));
-      }
+      // Input is legal?  Do an FP_ROUND_INREG.
+      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
+                           DAG.getValueType(VT));
       break;
     }
     break;
+
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
@@ -4043,14 +4028,24 @@
   case ISD::FCOPYSIGN:
     // These operators require that their input be fp extended.
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
-    case Expand: assert(0 && "not implemented");
-    case Legal:   Tmp1 = LegalizeOp(Node->getOperand(0)); break;
-    case Promote: Tmp1 = PromoteOp(Node->getOperand(0));  break;
+      case Legal:
+        Tmp1 = LegalizeOp(Node->getOperand(0));
+        break;
+      case Promote:
+        Tmp1 = PromoteOp(Node->getOperand(0));
+        break;
+      case Expand:
+        assert(0 && "not implemented");
     }
     switch (getTypeAction(Node->getOperand(1).getValueType())) {
-    case Expand: assert(0 && "not implemented");
-    case Legal:   Tmp2 = LegalizeOp(Node->getOperand(1)); break;
-    case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
+      case Legal:
+        Tmp2 = LegalizeOp(Node->getOperand(1));
+        break;
+      case Promote:
+        Tmp2 = PromoteOp(Node->getOperand(1));
+        break;
+      case Expand:
+        assert(0 && "not implemented");
     }
     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
     
@@ -4983,7 +4978,7 @@
     SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
                                      DAG.getConstant(0, Hi.getValueType()),
                                      ISD::SETLT);
-    SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
+    SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
     SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                       SignSet, Four, Zero);
     uint64_t FF = 0x5f800000ULL;
@@ -5105,8 +5100,7 @@
       // do nothing
       Result = Sub;
     } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
-      Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
-                           DAG.getIntPtrConstant(0));
+      Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
     } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
       Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
     }
@@ -5118,7 +5112,7 @@
   SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
                                    DAG.getConstant(0, Op0.getValueType()),
                                    ISD::SETLT);
-  SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
+  SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
   SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                     SignSet, Four, Zero);
 
@@ -5576,7 +5570,7 @@
       // Increment the pointer to the other half.
       unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
       Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                        DAG.getIntPtrConstant(IncrementSize));
+                        getIntPtrConstant(IncrementSize));
       SVOffset += IncrementSize;
       Alignment = MinAlign(Alignment, IncrementSize);
       Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
@@ -6529,7 +6523,7 @@
     Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
     unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     SVOffset += IncrementSize;
     Alignment = MinAlign(Alignment, IncrementSize);
     Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jan 18 14:09:08 2008
@@ -82,6 +82,10 @@
     return getTypeAction(VT) == Legal;
   }
   
+  SDOperand getIntPtrConstant(uint64_t Val) {
+    return DAG.getConstant(Val, TLI.getPointerTy());
+  }
+  
   /// PromotedNodes - For nodes that are below legal width, this map indicates
   /// what promoted value to use.
   DenseMap<SDOperand, SDOperand> PromotedNodes;

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Fri Jan 18 14:09:08 2008
@@ -253,7 +253,7 @@
     // Increment the pointer to the other half.
     unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
                      isVolatile, MinAlign(Alignment, IncrementSize));
 
@@ -300,7 +300,7 @@
     // Increment the pointer to the other half.
     unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
                         SVOffset+IncrementSize, NEVT,
                         isVolatile, MinAlign(Alignment, IncrementSize));
@@ -324,7 +324,7 @@
 
     // Increment the pointer to the other half.
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     // Load the rest of the low bits.
     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
                         SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
@@ -869,7 +869,7 @@
   SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
                                    DAG.getConstant(0, Hi.getValueType()),
                                    ISD::SETLT);
-  SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
+  SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
   SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
                                     SignSet, Four, Zero);
   uint64_t FF = 0x5f800000ULL;
@@ -1053,7 +1053,7 @@
                       SVOffset, isVolatile, Alignment);
 
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
     Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
                       isVolatile, MinAlign(Alignment, IncrementSize));
@@ -1076,7 +1076,7 @@
     // Increment the pointer to the other half.
     unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
                            SVOffset+IncrementSize, NEVT,
                            isVolatile, MinAlign(Alignment, IncrementSize));
@@ -1110,7 +1110,7 @@
 
     // Increment the pointer to the other half.
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                      DAG.getIntPtrConstant(IncrementSize));
+                      getIntPtrConstant(IncrementSize));
     // Store the lowest ExcessBits bits in the second half.
     Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
                            SVOffset+IncrementSize,

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp Fri Jan 18 14:09:08 2008
@@ -144,11 +144,8 @@
 
 SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
   // NOTE: Assumes input is legal.
-  if (N->getConstantOperandVal(1) == 0) 
-    return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
-                       N->getOperand(0), DAG.getValueType(N->getValueType(0)));
-  // If the precision discard isn't needed, just return the operand unrounded.
-  return N->getOperand(0);
+  return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
+                     N->getOperand(0), DAG.getValueType(N->getValueType(0)));
 }
 
 SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
@@ -356,8 +353,7 @@
 
 SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
   SDOperand Op = GetPromotedOp(N->getOperand(0));
-  return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
-                     DAG.getIntPtrConstant(0));
+  return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op);
 }
 
 SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp Fri Jan 18 14:09:08 2008
@@ -139,7 +139,7 @@
   Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
   unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
   Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                    DAG.getIntPtrConstant(IncrementSize));
+                    getIntPtrConstant(IncrementSize));
   SVOffset += IncrementSize;
   Alignment = MinAlign(Alignment, IncrementSize);
   Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
@@ -380,7 +380,7 @@
   
   // Increment the pointer to the other half.
   Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
-                    DAG.getIntPtrConstant(IncrementSize));
+                    getIntPtrConstant(IncrementSize));
   
   Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
                     isVol, MinAlign(Alignment, IncrementSize));

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jan 18 14:09:08 2008
@@ -710,11 +710,6 @@
   return Result;
 }
 
-SDOperand SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
-  return getConstant(Val, TLI.getPointerTy(), isTarget);
-}
-
-
 SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT,
                                       bool isTarget) {
   assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!");
@@ -1709,7 +1704,7 @@
   // Constant fold unary operations with a floating point constant operand.
   if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) {
     APFloat V = C->getValueAPF();    // make copy
-    if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
+    if (VT!=MVT::ppcf128 && Operand.getValueType()!=MVT::ppcf128) {
       switch (Opcode) {
       case ISD::FNEG:
         V.changeSign();
@@ -1754,13 +1749,13 @@
   switch (Opcode) {
   case ISD::TokenFactor:
     return Operand;         // Factor of one node?  No factor.
-  case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node");
+  case ISD::FP_ROUND:
   case ISD::FP_EXTEND:
     assert(MVT::isFloatingPoint(VT) &&
            MVT::isFloatingPoint(Operand.getValueType()) && "Invalid FP cast!");
     if (Operand.getValueType() == VT) return Operand;  // noop conversion.
     break;
-    case ISD::SIGN_EXTEND:
+  case ISD::SIGN_EXTEND:
     assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) &&
            "Invalid SIGN_EXTEND!");
     if (Operand.getValueType() == VT) return Operand;   // noop extension
@@ -1914,13 +1909,6 @@
            "Not rounding down!");
     break;
   }
-  case ISD::FP_ROUND:
-    assert(MVT::isFloatingPoint(VT) &&
-           MVT::isFloatingPoint(N1.getValueType()) &&
-           MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) &&
-           isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
-    if (N1.getValueType() == VT) return N1;  // noop conversion.
-    break;
   case ISD::AssertSext:
   case ISD::AssertZext:
   case ISD::SIGN_EXTEND_INREG: {

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jan 18 14:09:08 2008
@@ -483,6 +483,10 @@
                         const Value *SV, SDOperand Root,
                         bool isVolatile, unsigned Alignment);
 
+  SDOperand getIntPtrConstant(uint64_t Val) {
+    return DAG.getConstant(Val, TLI.getPointerTy());
+  }
+
   SDOperand getValue(const Value *V);
 
   void setValue(const Value *V, SDOperand NewN) {
@@ -673,10 +677,12 @@
       }
     }
   
-    if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
-      return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
+    if (MVT::isFloatingPoint(PartVT) &&
+        MVT::isFloatingPoint(ValueVT))
+      return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
 
-    if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
+    if (MVT::getSizeInBits(PartVT) == 
+        MVT::getSizeInBits(ValueVT))
       return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
 
     assert(0 && "Unknown mismatch!");
@@ -2157,7 +2163,7 @@
   // FPTrunc is never a no-op cast, no need to check
   SDOperand N = getValue(I.getOperand(0));
   MVT::ValueType DestVT = TLI.getValueType(I.getType());
-  setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
+  setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
 }
 
 void SelectionDAGLowering::visitFPExt(User &I){ 
@@ -2278,7 +2284,7 @@
         // N = N + Offset
         uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
         N = DAG.getNode(ISD::ADD, N.getValueType(), N,
-                        DAG.getIntPtrConstant(Offset));
+                        getIntPtrConstant(Offset));
       }
       Ty = StTy->getElementType(Field);
     } else {
@@ -2289,8 +2295,7 @@
         if (CI->getZExtValue() == 0) continue;
         uint64_t Offs = 
             TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
-        N = DAG.getNode(ISD::ADD, N.getValueType(), N,
-                        DAG.getIntPtrConstant(Offs));
+        N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
         continue;
       }
       
@@ -2315,7 +2320,7 @@
         continue;
       }
       
-      SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
+      SDOperand Scale = getIntPtrConstant(ElementSize);
       IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
       N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
     }
@@ -2343,7 +2348,7 @@
     AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
 
   AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
-                          DAG.getIntPtrConstant(TySize));
+                          getIntPtrConstant(TySize));
 
   // Handle alignment.  If the requested alignment is less than or equal to
   // the stack alignment, ignore it.  If the size is greater than or equal to
@@ -2356,12 +2361,12 @@
   // Round the size of the allocation up to the stack alignment size
   // by add SA-1 to the size.
   AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
-                          DAG.getIntPtrConstant(StackAlign-1));
+                          getIntPtrConstant(StackAlign-1));
   // Mask out the low bits for alignment purposes.
   AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
-                          DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
+                          getIntPtrConstant(~(uint64_t)(StackAlign-1)));
 
-  SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
+  SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
   const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
                                                     MVT::Other);
   SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
@@ -3810,7 +3815,7 @@
   // Scale the source by the type size.
   uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
   Src = DAG.getNode(ISD::MUL, Src.getValueType(),
-                    Src, DAG.getIntPtrConstant(ElementSize));
+                    Src, getIntPtrConstant(ElementSize));
 
   TargetLowering::ArgListTy Args;
   TargetLowering::ArgListEntry Entry;
@@ -3989,7 +3994,7 @@
         Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
       } else {
         assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
-        Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
+        Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
       }
       Ops.push_back(Op);
       break;

Modified: llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jan 18 14:09:08 2008
@@ -158,7 +158,7 @@
   // All operations default to being supported.
   memset(OpActions, 0, sizeof(OpActions));
   memset(LoadXActions, 0, sizeof(LoadXActions));
-  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
+  memset(&StoreXActions, 0, sizeof(StoreXActions));
   memset(&IndexedModeActions, 0, sizeof(IndexedModeActions));
   memset(&ConvertActions, 0, sizeof(ConvertActions));
 

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -125,8 +125,6 @@
   if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
     addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
     addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
-    
-    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
   }
   computeRegisterProperties();
 

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrInfo.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrInfo.td Fri Jan 18 14:09:08 2008
@@ -1404,6 +1404,14 @@
 def : ARMPat<(extloadi8  addrmode2:$addr),  (LDRB addrmode2:$addr)>;
 def : ARMPat<(extloadi16 addrmode3:$addr),  (LDRH addrmode3:$addr)>;
 
+// truncstore i1 -> truncstore i8
+def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst), 
+             (STRB GPR:$src, addrmode2:$dst)>;
+def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), 
+             (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
+def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), 
+             (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
+
 // smul* and smla*
 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
                  (SMULBB GPR:$a, GPR:$b)>;

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrThumb.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/ARM/ARMInstrThumb.td Fri Jan 18 14:09:08 2008
@@ -588,6 +588,10 @@
 def : ThumbPat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
 
+// truncstore i1 -> truncstore i8
+def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst), 
+               (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
+
 // Large immediate handling.
 
 // Two piece imms.

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/Alpha/AlphaISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/Alpha/AlphaISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -59,6 +59,8 @@
   setLoadXAction(ISD::SEXTLOAD, MVT::i8,  Expand);
   setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
 
+  setStoreXAction(MVT::i1, Promote);
+  
   //  setOperationAction(ISD::BRIND,        MVT::Other,   Expand);
   setOperationAction(ISD::BR_JT,        MVT::Other, Expand);
   setOperationAction(ISD::BR_CC,        MVT::Other, Expand);

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/CellSPU/SPUISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -137,21 +137,13 @@
   setLoadXAction(ISD::EXTLOAD,  MVT::i1, Promote);
   setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
   setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
-  setTruncStoreAction(MVT::i8, MVT::i1, Custom);
-  setTruncStoreAction(MVT::i16, MVT::i1, Custom);
-  setTruncStoreAction(MVT::i32, MVT::i1, Custom);
-  setTruncStoreAction(MVT::i64, MVT::i1, Custom);
-  setTruncStoreAction(MVT::i128, MVT::i1, Custom);
+  setStoreXAction(MVT::i1, Custom);
 
   setLoadXAction(ISD::EXTLOAD,  MVT::i8, Custom);
   setLoadXAction(ISD::SEXTLOAD, MVT::i8, Custom);
   setLoadXAction(ISD::ZEXTLOAD, MVT::i8, Custom);
-  setTruncStoreAction(MVT::i8  , MVT::i8, Custom);
-  setTruncStoreAction(MVT::i16 , MVT::i8, Custom);
-  setTruncStoreAction(MVT::i32 , MVT::i8, Custom);
-  setTruncStoreAction(MVT::i64 , MVT::i8, Custom);
-  setTruncStoreAction(MVT::i128, MVT::i8, Custom);
-  
+  setStoreXAction(MVT::i8, Custom);
+
   setLoadXAction(ISD::EXTLOAD,  MVT::i16, Custom);
   setLoadXAction(ISD::SEXTLOAD, MVT::i16, Custom);
   setLoadXAction(ISD::ZEXTLOAD, MVT::i16, Custom);

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/IA64/IA64ISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -193,8 +193,7 @@
             argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
                                                 MVT::f64);
             if (I->getType() == Type::FloatTy)
-              argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
-                                 DAG.getIntPtrConstant(0));
+              argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
             break;
           case MVT::i1: // NOTE: as far as C abi stuff goes,
                         // bools are just boring old ints

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -72,6 +72,9 @@
   setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
   setLoadXAction(ISD::SEXTLOAD, MVT::i1,  Promote);
 
+  // Store operations for i1 types must be promoted
+  setStoreXAction(MVT::i1, Promote);
+
   // Mips does not have these NodeTypes below.
   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsInstrInfo.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/Mips/MipsInstrInfo.td Fri Jan 18 14:09:08 2008
@@ -534,6 +534,8 @@
 def : Pat<(i32 (extloadi1  addr:$src)), (LBu addr:$src)>;
 def : Pat<(i32 (extloadi8  addr:$src)), (LBu addr:$src)>;
 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
+def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
+           (SB CPURegs:$src, addr:$addr)>;
 
 // some peepholes
 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -54,9 +54,10 @@
   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
   setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
   setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
-    
-  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-    
+  
+  // PowerPC does not have truncstore for i1.
+  setStoreXAction(MVT::i1, Promote);
+
   // PowerPC has pre-inc load and store's.
   setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
   setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
@@ -2170,7 +2171,7 @@
     SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
     SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
     if (Op.getValueType() == MVT::f32)
-      FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
+      FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
     return FP;
   }
   
@@ -2198,7 +2199,7 @@
   // FCFID it and return it.
   SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
   if (Op.getValueType() == MVT::f32)
-    FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
+    FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
   return FP;
 }
 
@@ -3169,8 +3170,7 @@
           Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
           DCI.AddToWorklist(Val.Val);
           if (N->getValueType(0) == MVT::f32) {
-            Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 
-                              DAG.getIntPtrConstant(0));
+            Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
             DCI.AddToWorklist(Val.Val);
           }
           return Val;

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/Sparc/SparcInstrInfo.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/Sparc/SparcInstrInfo.td Fri Jan 18 14:09:08 2008
@@ -774,3 +774,9 @@
 // zextload bool -> zextload byte
 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+
+// truncstore bool -> truncstore byte.
+def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
+          (STBrr ADDRrr:$addr, IntRegs:$src)>;
+def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr), 
+          (STBri ADDRri:$addr, IntRegs:$src)>;

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/TargetSelectionDAG.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/TargetSelectionDAG.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/TargetSelectionDAG.td Fri Jan 18 14:09:08 2008
@@ -551,6 +551,13 @@
 }]>;
 
 // truncstore fragments.
+def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
+                           (st node:$val, node:$ptr), [{
+  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+    return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
+           ST->getAddressingMode() == ISD::UNINDEXED;
+  return false;
+}]>;
 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
                            (st node:$val, node:$ptr), [{
   if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86ISelLowering.cpp?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86ISelLowering.cpp Fri Jan 18 14:09:08 2008
@@ -82,14 +82,6 @@
 
   setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
 
-  // We don't accept any truncstore of integer registers.  
-  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
-  setTruncStoreAction(MVT::i64, MVT::i16, Expand);
-  setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
-  setTruncStoreAction(MVT::i32, MVT::i16, Expand);
-  setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
-  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
-
   // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
   // operation.
   setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
@@ -646,8 +638,6 @@
       AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
     }
 
-    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-    
     // Custom lower v2i64 and v2f64 selects.
     setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
     setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
@@ -1192,7 +1182,8 @@
       SmallVector<SDOperand, 8> MemOps;
       SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
       SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
-                                  DAG.getIntPtrConstant(VarArgsGPOffset));
+                                  DAG.getConstant(VarArgsGPOffset,
+                                  getPointerTy()));
       for (; NumIntRegs != 6; ++NumIntRegs) {
         unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
                                   X86::GR64RegisterClass);
@@ -1200,12 +1191,12 @@
         SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
         MemOps.push_back(Store);
         FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
-                          DAG.getIntPtrConstant(8));
+                          DAG.getConstant(8, getPointerTy()));
       }
       
       // Now store the XMM (fp + vector) parameter registers.
       FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
-                        DAG.getIntPtrConstant(VarArgsFPOffset));
+                        DAG.getConstant(VarArgsFPOffset, getPointerTy()));
       for (; NumXMMRegs != 8; ++NumXMMRegs) {
         unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
                                   X86::VR128RegisterClass);
@@ -1213,7 +1204,7 @@
         SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
         MemOps.push_back(Store);
         FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
-                          DAG.getIntPtrConstant(16));
+                          DAG.getConstant(16, getPointerTy()));
       }
       if (!MemOps.empty())
           Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
@@ -1262,7 +1253,7 @@
                                     const CCValAssign &VA,
                                     SDOperand Chain,
                                     SDOperand Arg) {
-  SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
+  SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
   PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
   SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
   unsigned Flags    = cast<ConstantSDNode>(FlagsOp)->getValue();
@@ -1315,7 +1306,7 @@
       MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
   }
 
-  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
+  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
 
   SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
   if (IsTailCall) {
@@ -1449,7 +1440,7 @@
           // needs to be done because if we would lower the arguments directly
           // to their real stack slot we might end up overwriting each other.
           // Get source stack slot.
-          Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
+          Source = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
           if (StackPtr.Val == 0)
             StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
           Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
@@ -1510,8 +1501,8 @@
 
   if (IsTailCall) {
     Ops.push_back(Chain);
-    Ops.push_back(DAG.getIntPtrConstant(NumBytes));
-    Ops.push_back(DAG.getIntPtrConstant(0));
+    Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
+    Ops.push_back(DAG.getConstant(0, getPointerTy()));
     if (InFlag.Val)
       Ops.push_back(InFlag);
     Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
@@ -1569,8 +1560,9 @@
   
   // Returns a flag for retval copy to use.
   Chain = DAG.getCALLSEQ_END(Chain,
-                             DAG.getIntPtrConstant(NumBytes),
-                             DAG.getIntPtrConstant(NumBytesForCalleeToPush),
+                             DAG.getConstant(NumBytes, getPointerTy()),
+                             DAG.getConstant(NumBytesForCalleeToPush,
+                                             getPointerTy()),
                              InFlag);
   InFlag = Chain.getValue(1);
 
@@ -2740,7 +2732,7 @@
 
       if (ThisElt.Val)
         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
-                        DAG.getIntPtrConstant(i/2));
+                        DAG.getConstant(i/2, TLI.getPointerTy()));
     }
   }
 
@@ -2768,7 +2760,7 @@
         First = false;
       }
       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
-                      DAG.getIntPtrConstant(i));
+                      DAG.getConstant(i, TLI.getPointerTy()));
     }
   }
 
@@ -3577,7 +3569,7 @@
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
                       Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
-                       DAG.getIntPtrConstant(0));
+                       DAG.getConstant(0, getPointerTy()));
   } else if (MVT::getSizeInBits(VT) == 64) {
     unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
     if (Idx == 0)
@@ -3597,7 +3589,7 @@
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
                       Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
-                       DAG.getIntPtrConstant(0));
+                       DAG.getConstant(0, getPointerTy()));
   }
 
   return SDOperand();
@@ -3620,7 +3612,7 @@
     if (N1.getValueType() != MVT::i32)
       N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
     if (N2.getValueType() != MVT::i32)
-      N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
+      N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
     return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
   }
   return SDOperand();
@@ -4058,7 +4050,7 @@
   }
   // And if it is bigger, shrink it first.
   if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
-    Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
+    Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1);
     SrcVT = VT;
     SrcTy = MVT::getTypeForValueType(SrcVT);
   }
@@ -4091,7 +4083,7 @@
                           DAG.getConstant(32, MVT::i32));
     SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
     SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
-                          DAG.getIntPtrConstant(0));
+                          DAG.getConstant(0, getPointerTy()));
   }
 
   // Clear first operand sign bit.
@@ -4255,7 +4247,7 @@
   SDOperand Flag;
   
   MVT::ValueType IntPtr = getPointerTy();
-  MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
+  MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
 
   Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
   Flag = Chain.getValue(1);
@@ -4346,7 +4338,7 @@
     if (AVT > MVT::i8) {
       if (I) {
         unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
-        Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
+        Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
         BytesLeft = I->getValue() % UBytes;
       } else {
         assert(AVT >= MVT::i32 &&
@@ -4458,7 +4450,7 @@
   }
 
   unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
-  SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
+  SDOperand Count = DAG.getConstant(Size / UBytes, getPointerTy());
   BytesLeft = Size % UBytes;
 
   SDOperand InFlag(0, 0);
@@ -4587,21 +4579,24 @@
   MemOps.push_back(Store);
 
   // Store fp_offset
-  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(4, getPointerTy()));
   Store = DAG.getStore(Op.getOperand(0),
                        DAG.getConstant(VarArgsFPOffset, MVT::i32),
                        FIN, SV->getValue(), SV->getOffset());
   MemOps.push_back(Store);
 
   // Store ptr to overflow_arg_area
-  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(4, getPointerTy()));
   SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
   Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
                        SV->getOffset());
   MemOps.push_back(Store);
 
   // Store ptr to reg_save_area.
-  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(8, getPointerTy()));
   SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
   Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
                        SV->getOffset());
@@ -4629,9 +4624,9 @@
     if (i == 2)
       break;
     SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr, 
-                         DAG.getIntPtrConstant(8));
+                         DAG.getConstant(8, getPointerTy()));
     DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr, 
-                         DAG.getIntPtrConstant(8));
+                         DAG.getConstant(8, getPointerTy()));
   }
   return Chain;
 }
@@ -4762,7 +4757,7 @@
     
   SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
   return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 
-                     DAG.getIntPtrConstant(4));
+                     DAG.getConstant(4, getPointerTy()));
 }
 
 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
@@ -4771,7 +4766,7 @@
   if (Subtarget->is64Bit())
     return SDOperand();
   
-  return DAG.getIntPtrConstant(8);
+  return DAG.getConstant(8, getPointerTy());
 }
 
 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
@@ -4788,7 +4783,7 @@
                                     getPointerTy());
 
   SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
-                                    DAG.getIntPtrConstant(-4UL));
+                                    DAG.getConstant(-4UL, getPointerTy()));
   StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
   Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
   Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);

Modified: llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86InstrInfo.td?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/Apple/llvmCore-2010/lib/Target/X86/X86InstrInfo.td Fri Jan 18 14:09:08 2008
@@ -2598,6 +2598,11 @@
 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
           (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
 
+def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst), 
+          (MOV8mi addr:$dst, imm:$src)>;
+def : Pat<(truncstorei1 GR8:$src, addr:$dst), 
+          (MOV8mr addr:$dst, GR8:$src)>;
+
 // Comparisons.
 
 // TEST R,R is smaller than CMP R,0

Modified: llvm/branches/Apple/llvmCore-2010/test/CodeGen/X86/storetrunc-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/llvmCore-2010/test/CodeGen/X86/storetrunc-fp.ll?rev=46177&r1=46176&r2=46177&view=diff

==============================================================================
--- llvm/branches/Apple/llvmCore-2010/test/CodeGen/X86/storetrunc-fp.ll (original)
+++ llvm/branches/Apple/llvmCore-2010/test/CodeGen/X86/storetrunc-fp.ll Fri Jan 18 14:09:08 2008
@@ -1,8 +0,0 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep flds
-
-define void @foo(x86_fp80 %a, x86_fp80 %b, float* %fp) {
-	%c = add x86_fp80 %a, %b
-	%d = fptrunc x86_fp80 %c to float
-	store float %d, float* %fp
-	ret void
-}





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