[llvm-commits] [llvm] r45687 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/MachineInstr.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/Target/X86/X86CodeEmitter.cpp utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/DAGISelEmitter.cpp utils/TableGen/InstrInfoEmitter.cpp

Evan Cheng evan.cheng at apple.com
Tue Jan 8 14:24:46 PST 2008


Comments are accurate. Thx!

Evan
On Jan 6, 2008, at 9:19 PM, Chris Lattner wrote:

> Author: lattner
> Date: Sun Jan  6 23:19:29 2008
> New Revision: 45687
>
> URL: http://llvm.org/viewvc/llvm-project?rev=45687&view=rev
> Log:
> rename hasVariableOperands() -> isVariadic().  Add some comments.
> Evan, please review the comments I added to getNumDefs to make sure
> that they are accurate, thx.
>
> Modified:
>    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
>    llvm/trunk/lib/CodeGen/MachineInstr.cpp
>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
>    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
>    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
>    llvm/trunk/utils/TableGen/CodeGenInstruction.h
>    llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
>    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45687&r1=45686&r2=45687&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan  6  
> 23:19:29 2008
> @@ -125,9 +125,7 @@
> // block.
> const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
>
> -// M_VARIABLE_OPS - Set if this instruction can have a variable  
> number of extra
> -// operands in addition to the minimum number operands specified.
> -const unsigned M_VARIABLE_OPS          = 1 << 13;
> +const unsigned M_VARIADIC          = 1 << 13;
>
> // M_PREDICABLE - Set if this instruction has a predicate operand that
> // controls execution. It may be set to 'always'.
> @@ -141,8 +139,6 @@
> // (e.g. instructions with unique labels attached).
> const unsigned M_NOT_DUPLICABLE        = 1 << 16;
>
> -// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional  
> definition, e.g.
> -// ARM instructions which can set condition code if 's' bit is set.
> const unsigned M_HAS_OPTIONAL_DEF      = 1 << 17;
>
> // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side  
> effects that
> @@ -182,7 +178,7 @@
>   /// it is set. Returns -1 if it is not set.
>   int getOperandConstraint(unsigned OpNum,
>                            TOI::OperandConstraint Constraint) const {
> -    assert((OpNum < NumOperands || hasVariableOperands()) &&
> +    assert((OpNum < NumOperands || isVariadic()) &&
>            "Invalid operand # of TargetInstrInfo");
>     if (OpNum < NumOperands &&
>         (OpInfo[OpNum].Constraints & (1 << Constraint))) {
> @@ -202,18 +198,32 @@
>     return Name;
>   }
>
> +  /// getNumOperands - Return the number of declared  
> MachineOperands for this
> +  /// MachineInstruction.  Note that variadic (isVariadic() returns  
> true)
> +  /// instructions may have additional operands at the end of the  
> list, and note
> +  /// that the machine instruction may include implicit register  
> def/uses as
> +  /// well.
>   unsigned getNumOperands() const {
>     return NumOperands;
>   }
>
> +  /// getNumDefs - Return the number of MachineOperands that are  
> register
> +  /// definitions.  Register definitions always occur at the start  
> of the
> +  /// machine operand list.  This is the number of "outs" in  
> the .td file.
>   unsigned getNumDefs() const {
>     return NumDefs;
>   }
>
> -  bool hasVariableOperands() const {
> -    return Flags & M_VARIABLE_OPS;
> +  /// isVariadic - Return true if this instruction can have a  
> variable number of
> +  /// operands.  In this case, the variable operands will be after  
> the normal
> +  /// operands but before the implicit definitions and uses (if any  
> are
> +  /// present).
> +  bool isVariadic() const {
> +    return Flags & M_VARIADIC;
>   }
>
> +  /// hasOptionalDef - Set if this instruction has an optional  
> definition, e.g.
> +  /// ARM instructions which can set condition code if 's' bit is  
> set.
>   bool hasOptionalDef() const {
>     return Flags & M_HAS_OPTIONAL_DEF;
>   }
>
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Jan  6 23:19:29 2008
> @@ -488,8 +488,7 @@
> ///
> bool MachineInstr::OperandsComplete() const {
>   unsigned short NumOperands = TID->getNumOperands();
> -  if (TID->hasVariableOperands() == 0 &&
> -      getNumOperands()-NumImplicitOps >= NumOperands)
> +  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >=  
> NumOperands)
>     return true;  // Broken: we have all the operands of this  
> instruction!
>   return false;
> }
> @@ -498,7 +497,7 @@
> ///
> unsigned MachineInstr::getNumExplicitOperands() const {
>   unsigned NumOperands = TID->getNumOperands();
> -  if (TID->hasVariableOperands() == 0)
> +  if (!TID->isVariadic())
>     return NumOperands;
>
>   for (unsigned e = getNumOperands(); NumOperands != e; + 
> +NumOperands) {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Jan  6  
> 23:19:29 2008
> @@ -294,7 +294,7 @@
>         const TargetInstrDescriptor *II,
>         unsigned Op) {
>   if (Op >= II->getNumOperands()) {
> -    assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of  
> instruction");
> +    assert(II->isVariadic() && "Invalid operand # of instruction");
>     return NULL;
>   }
>   if (II->OpInfo[Op].isLookupPtrRegClass())
> @@ -678,7 +678,7 @@
>                           II.getImplicitDefs() != 0;
> #ifndef NDEBUG
>     assert((II.getNumOperands() == NumMIOperands ||
> -            HasPhysRegOuts || II.hasVariableOperands()) &&
> +            HasPhysRegOuts || II.isVariadic()) &&
>            "#operands for dag node doesn't match .td file!");
> #endif
>
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Sun Jan  6 23:19:29  
> 2008
> @@ -799,6 +799,5 @@
>     break;
>   }
>
> -  assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
> -         CurOp == NumOps && "Unknown encoding!");
> +  assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown  
> encoding!");
> }
>
> Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sun Jan  6  
> 23:19:29 2008
> @@ -99,7 +99,7 @@
>   mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
>   neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
>   hasOptionalDef = false;
> -  hasVariableNumberOfOperands = false;
> +  isVariadic = false;
>
>   if (mayHaveSideEffects && neverHasSideEffects)
>     throw R->getName() +
> @@ -159,7 +159,7 @@
>       else if (Rec->isSubClassOf("OptionalDefOperand"))
>         hasOptionalDef = true;
>     } else if (Rec->getName() == "variable_ops") {
> -      hasVariableNumberOfOperands = true;
> +      isVariadic = true;
>       continue;
>     } else if (!Rec->isSubClassOf("RegisterClass") &&
>                Rec->getName() != "ptr_rc")
>
> Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
> +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sun Jan  6  
> 23:19:29 2008
> @@ -99,7 +99,7 @@
>     bool isReMaterializable;
>     bool hasDelaySlot;
>     bool usesCustomDAGSchedInserter;
> -    bool hasVariableNumberOfOperands;
> +    bool isVariadic;
>     bool hasCtrlDep;
>     bool isNotDuplicable;
>     bool hasOptionalDef;
>
> Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Sun Jan  6 23:19:29  
> 2008
> @@ -835,7 +835,7 @@
>       if (InstPatNode && InstPatNode->getOperator()->getName() ==  
> "set") {
>         InstPatNode = InstPatNode->getChild(InstPatNode- 
> >getNumChildren()-1);
>       }
> -      bool HasVarOps     = isRoot && II.hasVariableNumberOfOperands;
> +      bool HasVarOps     = isRoot && II.isVariadic;
>       // FIXME: fix how we deal with physical register operands.
>       bool HasImpInputs  = isRoot && Inst.getNumImpOperands() > 0;
>       bool HasImpResults = isRoot && DstRegs.size() > 0;
>
> Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45687&r1=45686&r2=45687&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sun Jan  6  
> 23:19:29 2008
> @@ -320,9 +320,9 @@
>   if (Inst.hasOptionalDef)     OS << "|M_HAS_OPTIONAL_DEF";
>   if (Inst.usesCustomDAGSchedInserter)
>     OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
> -  if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
> -  if (Inst.mayHaveSideEffects)          OS << "| 
> M_MAY_HAVE_SIDE_EFFECTS";
> -  if (NeverHasSideEffects)              OS << "| 
> M_NEVER_HAS_SIDE_EFFECTS";
> +  if (Inst.isVariadic)         OS << "|M_VARIADIC";
> +  if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
> +  if (NeverHasSideEffects)     OS << "|M_NEVER_HAS_SIDE_EFFECTS";
>   OS << ", 0";
>
>   // Emit all of the target-specific flags...
>
>
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