[llvm-commits] [llvm] r45748 - in /llvm/trunk: include/llvm/Target/TargetInstrDesc.h utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp
Chris Lattner
sabre at nondot.org
Tue Jan 8 10:05:21 PST 2008
Author: lattner
Date: Tue Jan 8 12:05:21 2008
New Revision: 45748
URL: http://llvm.org/viewvc/llvm-project?rev=45748&view=rev
Log:
add a mayLoad property for machine instructions, a correlary to mayStore.
This is currently not set by anything.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrDesc.h
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=45748&r1=45747&r2=45748&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Tue Jan 8 12:05:21 2008
@@ -90,6 +90,7 @@
NotDuplicable,
DelaySlot,
SimpleLoad,
+ MayLoad,
MayStore,
NeverHasSideEffects,
MayHaveSideEffects,
@@ -308,6 +309,14 @@
//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//
+
+ /// mayLoad - Return true if this instruction could possibly read memory.
+ /// Instructions with this flag set are not necessarily simple load
+ /// instructions, they may load a value and modify it, for example.
+ bool mayLoad() const {
+ return Flags & (1 << TID::MayLoad);
+ }
+
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
@@ -317,8 +326,6 @@
return Flags & (1 << TID::MayStore);
}
- // TODO: mayLoad.
-
/// hasNoSideEffects - Return true if all instances of this instruction are
/// guaranteed to have no side effects other than:
/// 1. The register operands that are def/used by the MachineInstr.
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=45748&r1=45747&r2=45748&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Tue Jan 8 12:05:21 2008
@@ -84,6 +84,7 @@
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
isSimpleLoad = R->getValueAsBit("isSimpleLoad");
+ mayLoad = R->getValueAsBit("mayLoad");
mayStore = R->getValueAsBit("mayStore");
isImplicitDef= R->getValueAsBit("isImplicitDef");
bool isTwoAddress = R->getValueAsBit("isTwoAddress");
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=45748&r1=45747&r2=45748&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Tue Jan 8 12:05:21 2008
@@ -90,7 +90,7 @@
bool isBarrier;
bool isCall;
bool isSimpleLoad;
- bool mayStore;
+ bool mayLoad, mayStore;
bool isImplicitDef;
bool isPredicable;
bool isConvertibleToThreeAddress;
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45748&r1=45747&r2=45748&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Jan 8 12:05:21 2008
@@ -144,12 +144,12 @@
class InstAnalyzer {
const CodeGenDAGPatterns &CDP;
bool &mayStore;
- bool &isLoad;
+ bool &mayLoad;
bool &NeverHasSideEffects;
public:
InstAnalyzer(const CodeGenDAGPatterns &cdp,
- bool &maystore, bool &isload, bool &nhse)
- : CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
+ bool &maystore, bool &mayload, bool &nhse)
+ : CDP(cdp), mayStore(maystore), mayLoad(mayload), NeverHasSideEffects(nhse){
}
void Analyze(Record *InstRecord) {
@@ -166,9 +166,8 @@
private:
void AnalyzeNode(const TreePatternNode *N) {
- if (N->isLeaf()) {
+ if (N->isLeaf())
return;
- }
if (N->getOperator()->getName() != "set") {
// Get information about the SDNode for the operator.
@@ -191,11 +190,11 @@
};
void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
- bool &mayStore, bool &isLoad,
+ bool &mayStore, bool &mayLoad,
bool &NeverHasSideEffects) {
- mayStore = isLoad = NeverHasSideEffects = false;
+ mayStore = mayLoad = NeverHasSideEffects = false;
- InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
+ InstAnalyzer(CDP, mayStore, mayLoad,NeverHasSideEffects).Analyze(Inst.TheDef);
// InstAnalyzer only correctly analyzes mayStore so far.
if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
@@ -210,7 +209,7 @@
}
// These two override everything.
- isLoad = Inst.isSimpleLoad;
+ mayLoad = Inst.mayLoad;
NeverHasSideEffects = Inst.neverHasSideEffects;
#if 0
@@ -281,8 +280,8 @@
const OperandInfoMapTy &OpInfo,
std::ostream &OS) {
// Determine properties of the instruction from its pattern.
- bool mayStore, isSimpleLoad, NeverHasSideEffects;
- InferFromPattern(Inst, mayStore, isSimpleLoad, NeverHasSideEffects);
+ bool mayStore, mayLoad, NeverHasSideEffects;
+ InferFromPattern(Inst, mayStore, mayLoad, NeverHasSideEffects);
if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
std::cerr << "error: Instruction '" << Inst.TheDef->getName()
@@ -308,7 +307,8 @@
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|(1<<TID::Call)";
- if (isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
+ if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
+ if (mayLoad) OS << "|(1<<TID::MayLoad)";
if (mayStore) OS << "|(1<<TID::MayStore)";
if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
More information about the llvm-commits
mailing list