[llvm-commits] [llvm] r45219 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/extract_elt.ll

[Scott Michel]

Author: pingbak
Date: Wed Dec 19 15:17:42 2007
New Revision: 45219

URL: http://llvm.org/viewvc/llvm-project?rev=45219&view=rev
Log:
CellSPU testcase, extract_elt.ll: extract vector element.

Added:
    llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll
Modified:
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45219&r1=45218&r2=45219&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 15:17:42 2007
@@ -2101,7 +2101,7 @@
   }
 
   // Need to generate shuffle mask and extract:
-  int prefslot_begin, prefslot_end;
+  int prefslot_begin = -1, prefslot_end = -1;
   int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8;
 
   switch (VT) {
@@ -2123,6 +2123,9 @@
   }
   }
 
+  assert(prefslot_begin != -1 && prefslot_end != -1 &&
+	 "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
+
   for (int i = 0; i < 16; ++i) {
     // zero fill uppper part of preferred slot, don't care about the
     // other slots:
@@ -2134,7 +2137,7 @@
 	 ? 0x80
 	 : elt_byte + (i - prefslot_begin));
 
-      ShufMask[i] = DAG.getConstant(mask_val, MVT::i16);
+      ShufMask[i] = DAG.getConstant(mask_val, MVT::i8);
     } else 
       ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
   }

Added: llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll?rev=45219&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll Wed Dec 19 15:17:42 2007
@@ -0,0 +1,175 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
+; RUN: grep shufb %t1.s | count 27 &&
+; RUN: grep   lqa %t1.s | count 27 &&
+; RUN: grep   lqx %t2.s | count 27 &&
+; RUN: grep space %t1.s | count 8 &&
+; RUN: grep  byte %t1.s | count 424
+
+define i32 @i32_extract_0(<4 x i32> %v) {
+entry:
+  %a = extractelement <4 x i32> %v, i32 0
+  ret i32 %a
+}
+
+define i32 @i32_extract_1(<4 x i32> %v) {
+entry:
+  %a = extractelement <4 x i32> %v, i32 1
+  ret i32 %a
+}
+
+define i32 @i32_extract_2(<4 x i32> %v) {
+entry:
+  %a = extractelement <4 x i32> %v, i32 2
+  ret i32 %a
+}
+
+define i32 @i32_extract_3(<4 x i32> %v) {
+entry:
+  %a = extractelement <4 x i32> %v, i32 3
+  ret i32 %a
+}
+
+define i16 @i16_extract_0(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 0
+  ret i16 %a
+}
+
+define i16 @i16_extract_1(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 1
+  ret i16 %a
+}
+
+define i16 @i16_extract_2(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 2
+  ret i16 %a
+}
+
+define i16 @i16_extract_3(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 3
+  ret i16 %a
+}
+
+define i16 @i16_extract_4(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 4
+  ret i16 %a
+}
+
+define i16 @i16_extract_5(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 5
+  ret i16 %a
+}
+
+define i16 @i16_extract_6(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 6
+  ret i16 %a
+}
+
+define i16 @i16_extract_7(<8 x i16> %v) {
+entry:
+  %a = extractelement <8 x i16> %v, i32 7
+  ret i16 %a
+}
+
+define i8 @i8_extract_0(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 0
+  ret i8 %a
+}
+
+define i8 @i8_extract_1(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 1
+  ret i8 %a
+}
+
+define i8 @i8_extract_2(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 2
+  ret i8 %a
+}
+
+define i8 @i8_extract_3(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 3
+  ret i8 %a
+}
+
+define i8 @i8_extract_4(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 4
+  ret i8 %a
+}
+
+define i8 @i8_extract_5(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 5
+  ret i8 %a
+}
+
+define i8 @i8_extract_6(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 6
+  ret i8 %a
+}
+
+define i8 @i8_extract_7(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 7
+  ret i8 %a
+}
+
+define i8 @i8_extract_8(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 8
+  ret i8 %a
+}
+
+define i8 @i8_extract_9(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 9
+  ret i8 %a
+}
+
+define i8 @i8_extract_10(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 10
+  ret i8 %a
+}
+
+define i8 @i8_extract_11(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 11
+  ret i8 %a
+}
+
+define i8 @i8_extract_12(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 12
+  ret i8 %a
+}
+
+define i8 @i8_extract_13(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 13
+  ret i8 %a
+}
+
+define i8 @i8_extract_14(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 14
+  ret i8 %a
+}
+
+define i8 @i8_extract_15(<16 x i8> %v) {
+entry:
+  %a = extractelement <16 x i8> %v, i32 15
+  ret i8 %a
+}