[llvm-commits] [llvm] r44380 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h README.txt

[Chris Lattner]

Author: lattner
Date: Tue Nov 27 16:36:16 2007
New Revision: 44380

URL: http://llvm.org/viewvc/llvm-project?rev=44380&view=rev
Log:
implement a trivial readme entry.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
    llvm/trunk/lib/Target/ARM/README.txt

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=44380&r1=44379&r2=44380&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Nov 27 16:36:16 2007
@@ -262,6 +262,9 @@
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
 
+  // We have target-specific dag combine patterns for the following nodes:
+  // ARMISD::FMRRD  - No need to call setTargetDAGCombine
+  
   setStackPointerRegisterToSaveRestore(ARM::SP);
   setSchedulingPreference(SchedulingForRegPressure);
   setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
@@ -1510,6 +1513,27 @@
 //                           ARM Optimization Hooks
 //===----------------------------------------------------------------------===//
 
+/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
+static SDOperand PerformFMRRDCombine(SDNode *N, 
+                                     TargetLowering::DAGCombinerInfo &DCI) {
+  // fmrrd(fmdrr x, y) -> x,y
+  SDOperand InDouble = N->getOperand(0);
+  if (InDouble.getOpcode() == ARMISD::FMDRR)
+    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
+  return SDOperand();
+}
+
+SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
+                                               DAGCombinerInfo &DCI) const {
+  switch (N->getOpcode()) {
+  default: break;
+  case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
+  }
+  
+  return SDOperand();
+}
+
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=44380&r1=44379&r2=44380&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Nov 27 16:36:16 2007
@@ -78,6 +78,8 @@
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
     virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
         
+    SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+    
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,

Modified: llvm/trunk/lib/Target/ARM/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=44380&r1=44379&r2=44380&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/README.txt (original)
+++ llvm/trunk/lib/Target/ARM/README.txt Tue Nov 27 16:36:16 2007
@@ -574,21 +574,3 @@
 
 //===---------------------------------------------------------------------===//
 
-Easy ARM microoptimization (with -mattr=+vfp2):
-
-define i64 @i(double %X) {
-        %Y = bitcast double %X to i64
-        ret i64 %Y
-}
-
-compiles into:
-
-_i:
-        fmdrr d0, r0, r1
-        fmrrd r0, r1, d0
-        bx lr
-
-This just needs a target-specific dag combine to merge the two ARMISD nodes.
-
-
-//===---------------------------------------------------------------------===//