[llvm-commits] [llvm] r43168 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

[Chris Lattner]

Author: lattner
Date: Thu Oct 18 23:08:28 2007
New Revision: 43168

URL: http://llvm.org/viewvc/llvm-project?rev=43168&view=rev
Log:
comment fixes

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=43168&r1=43167&r2=43168&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Oct 18 23:08:28 2007
@@ -231,12 +231,12 @@
   }
 
   if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
-    // 64 bit PowerPC implementations can support i64 types directly
+    // 64-bit PowerPC implementations can support i64 types directly
     addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
     // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
     setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
   } else {
-    // 32 bit PowerPC wants to expand i64 shifts itself.
+    // 32-bit PowerPC wants to expand i64 shifts itself.
     setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
     setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
     setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
@@ -2105,7 +2105,7 @@
   assert(Op.getValueType() == MVT::ppcf128);
   SDNode *Node = Op.Val;
   assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
-  assert(Node->getOperand(0).Val->getOpcode()==ISD::BUILD_PAIR);
+  assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
   SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
   SDOperand Hi = Node->getOperand(0).Val->getOperand(1);