[llvm-commits] [llvm] r42959 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

[Dale Johannesen]

Author: johannes
Date: Sat Oct 13 20:58:32 2007
New Revision: 42959

URL: http://llvm.org/viewvc/llvm-project?rev=42959&view=rev
Log:
Fix type mismatch error in PPC Altivec (only causes
a problem when asserts are on).  From vecLib.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=42959&r1=42958&r2=42959&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Oct 13 20:58:32 2007
@@ -2570,14 +2570,14 @@
     if (SextVal >= 0 && SextVal <= 31) {
       SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
       SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
-      LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
+      LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
       return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
     }
     // Odd, in range [-31,-17]:  (vsplti C)+(vsplti -16).
     if (SextVal >= -31 && SextVal <= 0) {
       SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
       SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
-      LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
+      LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
       return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
     }
   }