[llvm-commits] [llvm] r42946 - in /llvm/trunk: include/llvm/Target/MRegisterInfo.h lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.h

[Evan Cheng]

Author: evancheng
Date: Fri Oct 12 21:35:06 2007
New Revision: 42946

URL: http://llvm.org/viewvc/llvm-project?rev=42946&view=rev
Log:
Change unfoldMemoryOperand(). User is now responsible for passing in the
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

Modified:
    llvm/trunk/include/llvm/Target/MRegisterInfo.h
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.h

Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=42946&r1=42945&r2=42946&view=diff

==============================================================================
--- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/MRegisterInfo.h Fri Oct 12 21:35:06 2007
@@ -567,7 +567,7 @@
   /// a a store or a load and a store into two or more instruction. If this is
   /// possible, returns true as well as the new instructions by reference.
   virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
-                                   SSARegMap *RegMap,
+                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
                                    SmallVector<MachineInstr*, 4> &NewMIs) const{
     return false;
   }

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=42946&r1=42945&r2=42946&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Oct 12 21:35:06 2007
@@ -1118,7 +1118,7 @@
 }
 
 bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
-                                          SSARegMap *RegMap,
+                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
                                   SmallVector<MachineInstr*, 4> &NewMIs) const {
   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
     MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
@@ -1128,6 +1128,13 @@
   unsigned Index = I->second.second & 0xf;
   bool HasLoad = I->second.second & (1 << 4);
   bool HasStore = I->second.second & (1 << 5);
+  if (UnfoldLoad && !HasLoad)
+    return false;
+  HasLoad &= UnfoldLoad;
+  if (UnfoldStore && !HasStore)
+    return false;
+  HasStore &= UnfoldStore;
+
   const TargetInstrDescriptor &TID = TII.get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
@@ -1149,10 +1156,8 @@
   }
 
   // Emit the load instruction.
-  unsigned LoadReg = 0;
   if (HasLoad) {
-    LoadReg = RegMap->createVirtualRegister(RC);
-    loadRegFromAddr(MF, LoadReg, AddrOps, RC, NewMIs);
+    loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
     if (HasStore) {
       // Address operands cannot be marked isKill.
       for (unsigned i = 1; i != 5; ++i) {
@@ -1164,27 +1169,29 @@
   }
 
   // Emit the data processing instruction.
-  MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
-  unsigned StoreReg = 0;
+  MachineInstr *DataMI = new MachineInstr (TID, true);
+  MachineInstrBuilder MIB(DataMI);
   const TargetRegisterClass *DstRC = 0;
   if (HasStore) {
     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
     DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
       ? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
-    StoreReg = RegMap->createVirtualRegister(RC);
-    MIB.addReg(StoreReg, true);
+    MIB.addReg(Reg, true);
   }
   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
     MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
-  if (LoadReg)
-    MIB.addReg(LoadReg);
+  MIB.addReg(Reg);
   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
     MIB = X86InstrAddOperand(MIB, AfterOps[i]);
+  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
+    MachineOperand &MO = ImpOps[i];
+    MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
+  }
   NewMIs.push_back(MIB);
 
   // Emit the store instruction.
   if (HasStore)
-    storeRegToAddr(MF, StoreReg, AddrOps, DstRC, NewMIs);
+    storeRegToAddr(MF, Reg, AddrOps, DstRC, NewMIs);
 
   return true;
 }

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=42946&r1=42945&r2=42946&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Fri Oct 12 21:35:06 2007
@@ -136,7 +136,7 @@
   /// a store or a load and a store into two or more instruction. If this is
   /// possible, returns true as well as the new instructions by reference.
   bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
-                           SSARegMap *RegMap,
+                           unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
                            SmallVector<MachineInstr*, 4> &NewMIs) const;
 
   bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,